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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-10 19:55:53 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 21:19:16 +0000 |
| commit | f76c12a3fcf0e181cfb7358d3972c55b3d7fb6fa (patch) | |
| tree | 493cd6f5de8e789d09f825a5897d9c65e178d0c0 /src | |
| parent | b8cd4b00497d74a4f28a22bad0f9b79ab88405e3 (diff) | |
| download | coreboot-f76c12a3fcf0e181cfb7358d3972c55b3d7fb6fa.tar.xz | |
mb/asus/p5ql-em: Fix S3 resume
The superio VSBGATE# functionality needs to be enabled for ram to be
powered during S3.
Change-Id: I7b827e025de7d5b53c587872238a411fc9c2e762
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36709
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/asus/p5ql-em/devicetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 8b5215e6e0..165340321b 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -138,7 +138,9 @@ chip northbridge/intel/x4x # Northbridge irq 0xe0 = 0xdf irq 0xf3 = 0x09 # RSVD SUSLED settings end - device pnp 2e.a off end # ACPI + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 + end device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 |