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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 17:53:38 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 12:42:40 +0000 |
| commit | f7c551cf6efe103688bb39563a7dca692431d766 (patch) | |
| tree | 4f54b279d7e2f6f87a4c207ad932459b6434dd4f /src | |
| parent | 7f87812c30ac5e4c3329911aec2ce52050a9abbb (diff) | |
| download | coreboot-f7c551cf6efe103688bb39563a7dca692431d766.tar.xz | |
soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND
The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops.
Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/lpss.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index d9027f5584..323d406d95 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -19,7 +19,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), |