diff options
| author | Richard Smith <smithbone@gmail.com> | 2006-08-25 16:14:31 +0000 |
|---|---|---|
| committer | Richard Smith <smithbone@gmail.com> | 2006-08-25 16:14:31 +0000 |
| commit | fa60e7f9d06d9a54e8bcc9e6f90eb3bc6ae4095e (patch) | |
| tree | 53fbecb678a20bb807575ea2e3bda18ac445aa7b /src | |
| parent | 64443b8c4970cc61ca4501d041d9e6983d02bef9 (diff) | |
| download | coreboot-fa60e7f9d06d9a54e8bcc9e6f90eb3bc6ae4095e.tar.xz | |
- USB P4 as host fix
This should make the USB P4 work as a USB host
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 26 |
2 files changed, 16 insertions, 12 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 06f9a6372b..68969974a7 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -706,6 +706,8 @@ /* SouthBridge Equates*/ /* MSR_SB and SB_SHIFT are located in CPU.inc*/ +#define MSR_SB_USB2_MEM_DES ((1<<16) + MSR_SB + 0x25) /* Hack to make USB P4 work */ + #define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ #define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 1c93a1e936..ff7763218e 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -157,19 +157,19 @@ static void southbridge_init(struct device *dev) volatile unsigned long* uocmux; unsigned long val; - printk_err("Base 0x%08x\n",USB2_SB_GLD_MSR_CAP); + + printk_err("DES 0x%08x\n",MSR_SB_USB2_MEM_DES); - msr = rdmsr(USB2_SB_GLD_MSR_CAP); - printk_err("CAP 0x%08x%08x\n", msr.hi,msr.lo); + msr = rdmsr(MSR_SB_USB2_MEM_DES); + printk_err("DES 0x%08x%08x\n", msr.hi,msr.lo); - msr = rdmsr(USB2_SB_GLD_MSR_OHCI_BASE); - printk_err("OHCI base 0x%08x%08x\n", msr.hi,msr.lo); + msr.hi = 0x400000fe; + msr.lo = 0x010fffff; - msr = rdmsr(USB2_SB_GLD_MSR_EHCI_BASE); - printk_err("EHCI base 0x%08x%08x\n", msr.hi,msr.lo); + wrmsr(MSR_SB_USB2_MEM_DES, msr); - msr = rdmsr(USB2_SB_GLD_MSR_DEVCTL_BASE); - printk_err("DevCtl base 0x%08x%08x\n", msr.hi,msr.lo); + msr = rdmsr(MSR_SB_USB2_MEM_DES); + printk_err("New DES 0x%08x%08x\n", msr.hi,msr.lo); msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE); printk_err("Old UOC Base 0x%08x%08x\n", msr.hi,msr.lo); @@ -185,12 +185,14 @@ static void southbridge_init(struct device *dev) val = *uocmux; printk_err("UOCMUX is 0x%lx\n",val); -#if 0 - val &= ~(0xc0); + + val &= ~(0x3); val |= 0x2; *uocmux = val; -#endif + + val = *uocmux; + printk_err("New UOCMUX is 0x%lx\n",val); } |