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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2020-03-09 12:56:30 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-03-11 14:42:13 +0000
commitfe2a4c1001dcb92947616213855feccf4495e479 (patch)
tree6f02e391731aec39d8e68b91df5d891e374c692d /src
parent6bc471461beb49ae0d489268cec799cb48d807a1 (diff)
downloadcoreboot-fe2a4c1001dcb92947616213855feccf4495e479.tar.xz
mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index d0006d64d7..60be8c9fab 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -175,6 +175,9 @@ chip soc/intel/cannonlake
register "tcc_offset" = "1"
+ # PCH Thermal Trip Temperature in deg C
+ register "common_soc_config.pch_thermal_trip" = "77"
+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {