soc/intel/skylake: Cleanup patch for Skylake SoC

Here is the list of items of code cleanup
1. Define TCO registers in smbus.h and not in pmc.h (as per EDS).
2. Include smbus.h wherever these TCO register defines were used.
3. Remove duplication of define in gpio_defs.h.
4. Remove unnecessary console.h include from memmap.h as no prints done.
5. Remove unnecessary comment from pch.c.

BUG=none
BRANCH=none
TEST=Built and boot kunimitsu.

Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16027
Tested-by: build bot (Jenkins)
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

8 files changed, 12 insertions, 16 deletions

diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index ca6455e496..8d5d4fec63 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -20,7 +20,7 @@
 #include <stdint.h>
 #include <elog.h>
 #include <soc/pm.h>
-#include <soc/pmc.h>
+#include <soc/smbus.h>
 
 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 6edec1ffd8..b37224d5e3 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -28,7 +28,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr.h>
 #include <soc/pm.h>
-#include <soc/pmc.h>
+#include <soc/smbus.h>
 #include <soc/spi.h>
 #include <soc/systemagent.h>
 #include <device/pci.h>
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 4008dfe31d..112db63e18 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -482,7 +482,6 @@
 	/* GPIOTXSTATE - Drive value onto pad */
 #define  GPIOTXSTATE_SHIFT	0
 #define  GPIOTXSTATE_MASK	0x1
-#define PAD_CFG_DW_OFFSET	0x400
 	/* TERM - termination control */
 #define  PAD_TERM_SHIFT		10
 #define  PAD_TERM_MASK		0xf
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 9c9b175285..10ea6ae894 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -99,14 +99,4 @@
 #define GBLRST_CAUSE0		0x124
 #define GBLRST_CAUSE1		0x128
 
-
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
-#define TCO1_STS			0x04
-#define TCO2_STS			0x06
-#define  TCO2_STS_SECOND_TO		0x02
-#define  TCO2_STS_BOOT		0x04
-#define TCO1_CNT			0x08
-#define  TCO_LOCK			(1 << 12)
-#define  TCO_TMR_HLT			(1 << 11)
-
 #endif
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index c395c8ed19..ff89f3ab28 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -27,6 +27,15 @@
 /* SMBUS TCO base address. */
 #define TCOBASE		0x50
 
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO1_STS			0x04
+#define TCO2_STS			0x06
+#define  TCO2_STS_SECOND_TO		0x02
+#define  TCO2_STS_BOOT		0x04
+#define TCO1_CNT			0x08
+#define  TCO_LOCK			(1 << 12)
+#define  TCO_TMR_HLT			(1 << 11)
+
 /* SMBus I/O bits. */
 #define SMBHSTSTAT		0x0
 #define SMBHSTCTL		0x2
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index f7db86d0a0..6af13714a0 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -17,7 +17,6 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <chip.h>
-#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/msr.h>
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c
index 7c07b07009..ed64c8f66c 100644
--- a/src/soc/intel/skylake/pch.c
+++ b/src/soc/intel/skylake/pch.c
@@ -84,8 +84,6 @@ void pch_enable_dev(device_t dev)
 		reg32 &= ~(PCI_COMMAND_MASTER |
 			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		pci_write_config32(dev, PCI_COMMAND, reg32);
-
-		/* Disable this device if possible */
 	} else {
 		/* Enable SERR */
 		reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index cf75ccb750..1305062e5b 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -27,6 +27,7 @@
 #include <string.h>
 #include <soc/iomap.h>
 #include <soc/pmc.h>
+#include <soc/smbus.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>