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| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-13 23:37:22 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@google.com> | 2019-12-15 01:20:25 +0000 |
| commit | 1a5c3bb7fa56378664ce221cd749f118ef6a09f6 (patch) | |
| tree | 3435e31441dcde6375af86a74a29feb1671ecb59 /src | |
| parent | 7176a54c2b4c1a95219c5ab9e7b7b12a8ab6b0e2 (diff) | |
| download | coreboot-1a5c3bb7fa56378664ce221cd749f118ef6a09f6.tar.xz | |
mainboard/google/puff: Toggle on DqPinsInterleaved
BRANCH=none
BUG=b:146172098
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/romstage_spd_smbus.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 74d59a59f5..9073744850 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -45,6 +45,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ memcfg.vref_ca_config = 2; + memcfg.dq_pins_interleaved = 1; cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } |