diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-01-20 21:32:37 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-01-20 21:32:37 +0000 |
| commit | 20b261dacf56a0bf09a74931cd511537b79b6983 (patch) | |
| tree | b5526c469163150d6caf48f3fc00695284c0a53a /src | |
| parent | c5983305ef67f2f7df81945ae5508fdf2da6c5ea (diff) | |
| download | coreboot-20b261dacf56a0bf09a74931cd511537b79b6983.tar.xz | |
Fix register typo for core 2 cpus (trivial)
This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 2395f4d4fc..d04274046d 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -39,7 +39,7 @@ cache_as_ram: movl %eax, (%esi) /* Disable prefetchers */ - movl $0x01a0, %eax + movl $0x01a0, %ecx rdmsr orl $((1 << 9) | (1 << 19)), %eax orl $((1 << 5) | (1 << 7)), %edx |