diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-02 23:51:09 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-04-14 13:26:01 +0200 |
| commit | 2f6b52e3a0c09988d6e0aef4d7ef4268b41c09a2 (patch) | |
| tree | c96b1b884a588a6d96049cbb8d5999250889bca4 /src | |
| parent | f13e2501525f0025b03f4b2ee3487999bb0ade2b (diff) | |
| download | coreboot-2f6b52e3a0c09988d6e0aef4d7ef4268b41c09a2.tar.xz | |
nb/intel/i945: Fix PEG port on 945gc
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).
Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.
What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.
TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.
Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18549
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 20 |
2 files changed, 13 insertions, 10 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 0a2c99e51e..45501d1f53 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -939,7 +939,8 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - i945_setup_pci_express_x16(); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0499b48ee9..1f07425d6c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2576,17 +2576,19 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32; - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (i945_silicon_revision() > 1) { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0); - MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) = 0x1010 | peg_bits; + } else { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0); - /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010 | peg_bits; + } } reg16 = MCHBAR16(UPMC2); |