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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-23 10:07:16 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-24 10:40:40 +0000
commit346d201d73d51ae0a037f64b1bc6d530745b5d4a (patch)
treea6409d052902e76c4a87a9e34837c18a945fccb9 /src
parentcf32fd172928467ac5bbd4fb372b71230c81cf12 (diff)
downloadcoreboot-346d201d73d51ae0a037f64b1bc6d530745b5d4a.tar.xz
nb/intel/i945: Use DEBUG_RAM_SETUP
Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asus/p5gc-mx/romstage.c5
-rw-r--r--src/mainboard/getac/p470/romstage.c5
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c5
-rw-r--r--src/mainboard/ibase/mb899/romstage.c5
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c5
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c5
-rw-r--r--src/mainboard/lenovo/t60/romstage.c5
-rw-r--r--src/mainboard/lenovo/x60/romstage.c5
-rw-r--r--src/mainboard/lenovo/z61t/romstage.c5
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c5
-rw-r--r--src/northbridge/intel/i945/early_init.c18
-rw-r--r--src/northbridge/intel/i945/i945.h1
-rw-r--r--src/northbridge/intel/i945/raminit.c2
-rw-r--r--src/northbridge/intel/i945/raminit.h4
14 files changed, 23 insertions, 52 deletions
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index ffb3bf9ea7..a93009f5db 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -220,9 +220,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 423b4e869b..461e3946e6 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -271,9 +271,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index b2d4bb45aa..d23df35feb 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -172,9 +172,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 1257fa5b4c..49bb1e5634 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -231,9 +231,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 18a772171d..6cb24a6786 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -151,9 +151,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 52432a0cbe..394522cf2d 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -279,9 +279,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 070ee5951e..0ca690b849 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -208,9 +208,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 39e0ed57ac..e655ddf0e0 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -211,9 +211,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 45cd9ecab4..0c1d7b9bf7 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -209,9 +209,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index dbc4b6cb7b..46ef808159 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -244,9 +244,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d3ed27745d..08dd6752d6 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -940,22 +940,8 @@ void i945_late_initialization(int s3resume)
i945_setup_root_complex_topology();
-#if !CONFIG(HAVE_ACPI_RESUME)
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG(DEBUG_RAM_SETUP)
- sdram_dump_mchbar_registers();
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
- }
-#endif
-#endif
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ sdram_dump_mchbar_registers();
MCHBAR16(SSKPD) = 0xCAFE;
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 8c082416bc..ebcc8bcb19 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -375,6 +375,7 @@ void print_pci_devices(void);
void dump_pci_device(unsigned int dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
+void sdram_dump_mchbar_registers(void);
u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a93cf1e718..05b577787d 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -96,7 +96,6 @@ static void ram_read32(u32 offset)
read32((void *)offset);
}
-#if CONFIG(DEBUG_RAM_SETUP)
void sdram_dump_mchbar_registers(void)
{
int i;
@@ -108,7 +107,6 @@ void sdram_dump_mchbar_registers(void)
printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
}
}
-#endif
static int memclk(void)
{
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 2d1eee6947..e9e66d13e1 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -69,8 +69,4 @@ void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path, const u8 *sdram_addresses);
int fixup_i945_errata(void);
void udelay(u32 us);
-
-#if CONFIG(DEBUG_RAM_SETUP)
-void sdram_dump_mchbar_registers(void);
-#endif
#endif /* RAMINIT_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 10:14:21 +0000