diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-03-14 16:42:33 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-03-15 19:48:57 +0100 |
| commit | 57e9e3be5fe3a68c8ccedc85e673f091aaf8ff58 (patch) | |
| tree | 12f56b1512a7037e755f36b6e504eb962fe40062 /src | |
| parent | 86db46987176b6e78852d62042046e4af458e71a (diff) | |
| download | coreboot-57e9e3be5fe3a68c8ccedc85e673f091aaf8ff58.tar.xz | |
google/eve: Apply default AC/DC loadline settings
Set the AC and DC loadline values based on the KBL-Y 2+2 defaults
that are applied by FSP. These will be tuned later and are exposed
as defaults so the engineers know what to start with.
BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values
Change-Id: Ieae4f2b201d8210e75bdb9438070a3a2e1fda6b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 22b49d7116..76ef17c610 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -74,6 +74,8 @@ chip soc/intel/skylake #| ImonOffset | 0 | 0 | 0 | 0 | #| IccMax | 4A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 17.9 | 5.9 | 5.7 | 5.7 | + #| DcLoadline | 14 | 4.7 | 4.2 | 4.2 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, @@ -86,6 +88,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(4), .voltage_limit = 1520, + .ac_loadline = 1790, + .dc_loadline = 1400, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -99,6 +103,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 590, + .dc_loadline = 470, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -112,6 +118,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -125,6 +133,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 420, }" # Enable Root port 1 with SRCCLKREQ1# |