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| author | Kane Chen <kane.chen@intel.com> | 2018-11-15 17:48:48 +0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-11-27 14:38:42 +0000 |
| commit | 5ebcea3aaaa3cd358bc5bccaa156b13a6ef25df6 (patch) | |
| tree | 3d0eb7d8b68c631aa14754749aae1b3038250459 /src | |
| parent | 8f6af1cc52e2be4950b3e39f7772fc34af550e69 (diff) | |
| download | coreboot-5ebcea3aaaa3cd358bc5bccaa156b13a6ef25df6.tar.xz | |
mainboard/google/reef: Bump mainboard mem version
This change is to bump fsp_memory_mainboard_version in order to
trigger MRC full training
BUG=b:119481870
CQ-DEPEND=CL:*716558
BRANCH=reef, coral
TEST=make sure MRC retraining is triggered and the MRC cache is
updated to newer version.
Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/29647
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/memory.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index a0aad9ecd8..f298cae95e 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -17,6 +17,7 @@ #include <gpio.h> #include <soc/meminit.h> #include <variant/gpio.h> +#include <fsp/api.h> const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ @@ -167,3 +168,8 @@ size_t __weak variant_memory_sku(void) * exist. */ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); } + +uint8_t fsp_memory_mainboard_version(void) +{ + return 1; +} |