coreboot rush: Add dram init code

Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.

BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5

Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

12 files changed, 2683 insertions, 0 deletions

diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 4c6273f99f..746af11392 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -34,5 +34,6 @@ bootblock-y += reset.c
 
 romstage-y += romstage.c
 romstage-y += reset.c
+romstage-y += sdram_configs.c
 
 ramstage-y += mainboard.c
\ No newline at end of file
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index f0de9c0dfb..9db52989f7 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -22,6 +22,9 @@
 #include <console/console.h>
 #include <arch/exception.h>
 
+#include "sdram_configs.h"
+#include <soc/nvidia/tegra132/sdram.h>
+
 void main(void)
 {
 	void *entry;
@@ -31,6 +34,10 @@ void main(void)
 
 	printk(BIOS_INFO, "T132: romstage here\n");
 
+	sdram_init(get_sdram_config());
+
+	printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
+
 	while (1);
 
         entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
diff --git a/src/mainboard/google/rush/sdram_configs.c b/src/mainboard/google/rush/sdram_configs.c
new file mode 100644
index 0000000000..18386ac53e
--- /dev/null
+++ b/src/mainboard/google/rush/sdram_configs.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra132/sdram.h>
+#include "sdram_configs.h"
+
+static struct sdram_params sdram_configs[] = {
+#include "bct/sdram-hynix-2GB-924.inc"			/* ram_code = 0000 */
+#include "bct/sdram-hynix-4GB-792.inc"			/* ram_code = 0001 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0010 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0011 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0100 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0101 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0110 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0111 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1000 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1001 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1010 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1011 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1100 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1101 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1110 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1111 */
+};
+
+const struct sdram_params *get_sdram_config()
+{
+	uint32_t ramcode = sdram_get_ram_code();
+	/*
+	 * If we need to apply some special hacks to RAMCODE mapping (ex, by
+	 * board_id), do that now.
+	 */
+
+	printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
+	if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
+	    sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused)
+		die("Invalid RAMCODE.");
+
+	return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/rush/sdram_configs.h b/src/mainboard/google/rush/sdram_configs.h
new file mode 100644
index 0000000000..e00e9ca04c
--- /dev/null
+++ b/src/mainboard/google/rush/sdram_configs.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
+#define __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
+
+#include <soc/nvidia/tegra132/sdram_param.h>
+
+/* Loads SDRAM configurations for current system. */
+const struct sdram_params *get_sdram_config(void);
+
+#endif  /* __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__ */
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 7e9aed820a..a8b9bdc139 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -43,6 +43,10 @@ config ROMSTAGE_BASE
 	hex
 	default 0x4002c000
 
+config SYS_SDRAM_BASE
+	hex
+	default 0x80000000
+
 config RAMSTAGE_BASE
 	hex
 	default 0x80200000
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index abcdfd599e..855ef24832 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -24,6 +24,8 @@ romstage-y += spi.c
 romstage-y += i2c.c
 romstage-y += dma.c
 romstage-y += monotonic_timer.c
+romstage-y += sdram.c
+romstage-y += sdram_lp0.c
 romstage-y += ../tegra/gpio.c
 romstage-y += ../tegra/i2c.c
 romstage-y += ../tegra/pinmux.c
diff --git a/src/soc/nvidia/tegra132/emc.h b/src/soc/nvidia/tegra132/emc.h
new file mode 100644
index 0000000000..2aa814fc41
--- /dev/null
+++ b/src/soc/nvidia/tegra132/emc.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_EMC_H__
+#define __SOC_NVIDIA_TEGRA132_EMC_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+enum {
+	EMC_PIN_RESET_MASK = 1 << 8,
+	EMC_PIN_RESET_ACTIVE = 0 << 8,
+	EMC_PIN_RESET_INACTIVE = 1 << 8,
+	EMC_PIN_DQM_MASK = 1 << 4,
+	EMC_PIN_DQM_NORMAL = 0 << 4,
+	EMC_PIN_DQM_INACTIVE = 1 << 4,
+	EMC_PIN_CKE_MASK = 1 << 0,
+	EMC_PIN_CKE_POWERDOWN = 0 << 0,
+	EMC_PIN_CKE_NORMAL = 1 << 0,
+
+	EMC_REF_CMD_MASK = 1 << 0,
+	EMC_REF_CMD_REFRESH = 1 << 0,
+	EMC_REF_NORMAL_MASK = 1 << 1,
+	EMC_REF_NORMAL_INIT = 0 << 1,
+	EMC_REF_NORMAL_ENABLED = 1 << 1,
+	EMC_REF_NUM_SHIFT = 8,
+	EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT,
+	EMC_REF_DEV_SELECTN_SHIFT = 30,
+	EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT,
+
+	EMC_REFCTRL_REF_VALID_MASK = 1 << 31,
+	EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31,
+	EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31,
+
+	EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1,
+	EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2,
+	EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3,
+
+	EMC_NOP_NOP_CMD_SHIFT = 0,
+	EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT,
+	EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30,
+	EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT,
+
+	EMC_TIMING_CONTROL_TIMING_UPDATE = 1,
+};
+
+struct tegra_emc_regs {
+	uint32_t intstatus;		/* 0x0 */
+	uint32_t intmask;		/* 0x4 */
+	uint32_t dbg;			/* 0x8 */
+	uint32_t cfg;			/* 0xc */
+	uint32_t adr_cfg;		/* 0x10 */
+	uint32_t rsvd_0x14[3];		/* 0x14 */
+
+	uint32_t refctrl;		/* 0x20 */
+	uint32_t pin;			/* 0x24 */
+	uint32_t timing_control;	/* 0x28 */
+	uint32_t rc;			/* 0x2c */
+	uint32_t rfc;			/* 0x30 */
+	uint32_t ras;			/* 0x34 */
+	uint32_t rp;			/* 0x38 */
+	uint32_t r2w;			/* 0x3c */
+	uint32_t w2r;			/* 0x40 */
+	uint32_t r2p;			/* 0x44 */
+	uint32_t w2p;			/* 0x48 */
+	uint32_t rd_rcd;		/* 0x4c */
+	uint32_t wr_rcd;		/* 0x50 */
+	uint32_t rrd;			/* 0x54 */
+	uint32_t rext;			/* 0x58 */
+	uint32_t wdv;			/* 0x5c */
+	uint32_t quse;			/* 0x60 */
+	uint32_t qrst;			/* 0x64 */
+	uint32_t qsafe;			/* 0x68 */
+	uint32_t rdv;			/* 0x6c */
+	uint32_t refresh;		/* 0x70 */
+	uint32_t burst_refresh_num;	/* 0x74 */
+	uint32_t pdex2wr;		/* 0x78 */
+	uint32_t pdex2rd;		/* 0x7c */
+	uint32_t pchg2pden;		/* 0x80 */
+	uint32_t act2pden;		/* 0x84 */
+	uint32_t ar2pden;		/* 0x88 */
+	uint32_t rw2pden;		/* 0x8c */
+	uint32_t txsr;			/* 0x90 */
+	uint32_t tcke;			/* 0x94 */
+	uint32_t tfaw;			/* 0x98 */
+	uint32_t trpab;			/* 0x9c */
+	uint32_t tclkstable;		/* 0xa0 */
+	uint32_t tclkstop;		/* 0xa4 */
+	uint32_t trefbw;		/* 0xa8 */
+	uint32_t rsvd_0xac[1];		/* 0xac */
+	uint32_t odt_write;		/* 0xb0 */
+	uint32_t odt_read;		/* 0xb4 */
+	uint32_t wext;			/* 0xb8 */
+	uint32_t ctt;			/* 0xbc */
+	uint32_t rfc_slr;		/* 0xc0 */
+	uint32_t mrs_wait_cnt2;		/* 0xc4 */
+	uint32_t mrs_wait_cnt;		/* 0xc8 */
+	uint32_t mrs;			/* 0xcc */
+	uint32_t emrs;			/* 0xd0 */
+	uint32_t ref;			/* 0xd4 */
+	uint32_t pre;			/* 0xd8 */
+	uint32_t nop;			/* 0xdc */
+	uint32_t self_ref;		/* 0xe0 */
+	uint32_t dpd;			/* 0xe4 */
+	uint32_t mrw;			/* 0xe8 */
+	uint32_t mrr;			/* 0xec */
+	uint32_t cmdq;			/* 0xf0 */
+	uint32_t mc2emcq;		/* 0xf4 */
+	uint32_t xm2dqspadctrl3;	/* 0xf8 */
+	uint32_t rsvd_0xfc[1];		/* 0xfc */
+	uint32_t fbio_spare;		/* 0x100 */
+	uint32_t fbio_cfg5;		/* 0x104 */
+	uint32_t fbio_wrptr_eq_2;	/* 0x108 */
+	uint32_t rsvd_0x10c[2];		/* 0x10c */
+
+	uint32_t fbio_cfg6;		/* 0x114 */
+	uint32_t rsvd_0x118[2];		/* 0x118 */
+
+	uint32_t cfg_rsv;		/* 0x120 */
+	uint32_t acpd_control;		/* 0x132 */
+	uint32_t rsvd_0x128[1];		/* 0x128 */
+	uint32_t emrs2;			/* 0x12c */
+	uint32_t emrs3;			/* 0x130 */
+	uint32_t mrw2;			/* 0x134 */
+	uint32_t mrw3;			/* 0x138 */
+	uint32_t mrw4;			/* 0x13c */
+	uint32_t clken_override;	/* 0x140 */
+	uint32_t r2r;			/* 0x144 */
+	uint32_t w2w;			/* 0x148 */
+	uint32_t einput;		/* 0x14c */
+	uint32_t einput_duration;	/* 0x150 */
+	uint32_t puterm_extra;		/* 0x154 */
+	uint32_t tckesr;		/* 0x158 */
+	uint32_t tpd;			/* 0x15c */
+	uint32_t rsvd_0x160[81];		/* 0x160 */
+
+	uint32_t auto_cal_config;	/* 0x2a4 */
+	uint32_t auto_cal_interval;	/* 0x2a8 */
+	uint32_t auto_cal_status;	/* 0x2ac */
+	uint32_t req_ctrl;		/* 0x2b0 */
+	uint32_t status;		/* 0x2b4 */
+	uint32_t cfg_2;			/* 0x2b8 */
+	uint32_t cfg_dig_dll;		/* 0x2bc */
+	uint32_t cfg_dig_dll_period;	/* 0x2c0 */
+	uint32_t rsvd_0x2c4[1];		/* 0x2c4 */
+	uint32_t dig_dll_status;	/* 0x2c8 */
+	uint32_t rdv_mask;		/* 0x2cc */
+	uint32_t wdv_mask;		/* 0x2d0 */
+	uint32_t rsvd_0x2d4[1];		/* 0x2d4 */
+	uint32_t ctt_duration;		/* 0x2d8 */
+	uint32_t ctt_term_ctrl;		/* 0x2dc */
+	uint32_t zcal_interval;		/* 0x2e0 */
+	uint32_t zcal_wait_cnt;		/* 0x2e4 */
+	uint32_t zcal_mrw_cmd;		/* 0x2e8 */
+	uint32_t zq_cal;		/* 0x2ec */
+	uint32_t xm2cmdpadctrl;		/* 0x2f0 */
+	uint32_t xm2cmdpadctrl2;	/* 0x2f4 */
+	uint32_t xm2dqspadctrl;		/* 0x2f8 */
+	uint32_t xm2dqspadctrl2;	/* 0x2fc */
+	uint32_t xm2dqpadctrl;		/* 0x300 */
+	uint32_t xm2dqpadctrl2;		/* 0x304 */
+	uint32_t xm2clkpadctrl;		/* 0x308 */
+	uint32_t xm2comppadctrl;	/* 0x30c */
+	uint32_t xm2vttgenpadctrl;	/* 0x310 */
+	uint32_t xm2vttgenpadctrl2;	/* 0x314 */
+	uint32_t xm2vttgenpadctrl3;	/* 0x318 */
+	uint32_t emcpaden;		/* 0x31c */
+	uint32_t xm2dqspadctrl4;	/* 0x320 */
+	uint32_t scratch0;		/* 0x324 */
+	uint32_t dll_xform_dqs0;	/* 0x328 */
+	uint32_t dll_xform_dqs1;	/* 0x32c */
+	uint32_t dll_xform_dqs2;	/* 0x330 */
+	uint32_t dll_xform_dqs3;	/* 0x334 */
+	uint32_t dll_xform_dqs4;	/* 0x338 */
+	uint32_t dll_xform_dqs5;	/* 0x33c */
+	uint32_t dll_xform_dqs6;	/* 0x340 */
+	uint32_t dll_xform_dqs7;	/* 0x344 */
+	uint32_t dll_xform_quse0;	/* 0x348 */
+	uint32_t dll_xform_quse1;	/* 0x34c */
+	uint32_t dll_xform_quse2;	/* 0x350 */
+	uint32_t dll_xform_quse3;	/* 0x354 */
+	uint32_t dll_xform_quse4;	/* 0x358 */
+	uint32_t dll_xform_quse5;	/* 0x35c */
+	uint32_t dll_xform_quse6;	/* 0x360 */
+	uint32_t dll_xform_quse7;	/* 0x364 */
+	uint32_t dll_xform_dq0;		/* 0x368 */
+	uint32_t dll_xform_dq1;		/* 0x36c */
+	uint32_t dll_xform_dq2;		/* 0x370 */
+	uint32_t dll_xform_dq3;		/* 0x374 */
+	uint32_t dli_rx_trim0;		/* 0x378 */
+	uint32_t dli_rx_trim1;		/* 0x37c */
+	uint32_t dli_rx_trim2;		/* 0x380 */
+	uint32_t dli_rx_trim3;		/* 0x384 */
+	uint32_t dli_rx_trim4;		/* 0x388 */
+	uint32_t dli_rx_trim5;		/* 0x38c */
+	uint32_t dli_rx_trim6;		/* 0x390 */
+	uint32_t dli_rx_trim7;		/* 0x394 */
+	uint32_t dli_tx_trim0;		/* 0x398 */
+	uint32_t dli_tx_trim1;		/* 0x39c */
+	uint32_t dli_tx_trim2;		/* 0x3a0 */
+	uint32_t dli_tx_trim3;		/* 0x3a4 */
+	uint32_t dli_trim_txdqs0;	/* 0x3a8 */
+	uint32_t dli_trim_txdqs1;	/* 0x3ac */
+	uint32_t dli_trim_txdqs2;	/* 0x3b0 */
+	uint32_t dli_trim_txdqs3;	/* 0x3b4 */
+	uint32_t dli_trim_txdqs4;	/* 0x3b8 */
+	uint32_t dli_trim_txdqs5;	/* 0x3bc */
+	uint32_t dli_trim_txdqs6;	/* 0x3c0 */
+	uint32_t dli_trim_txdqs7;	/* 0x3c4 */
+	uint32_t rsvd_0x3c8[1];		/* 0x3c8 */
+	uint32_t stall_then_exe_after_clkchange;	/* 0x3cc */
+	uint32_t rsvd_0x3d0[1];		/* 0x3d0 */
+	uint32_t auto_cal_clk_status;	/* 0x3d4 */
+	uint32_t sel_dpd_ctrl;		/* 0x3d8 */
+	uint32_t pre_refresh_req_cnt;	/* 0x3dc */
+	uint32_t dyn_self_ref_control;	/* 0x3e0 */
+	uint32_t txsrdll;		/* 0x3e4 */
+	uint32_t ccfifo_addr;		/* 0x3e8 */
+	uint32_t ccfifo_data;		/* 0x3ec */
+	uint32_t ccfifo_status;		/* 0x3f0 */
+	uint32_t cdb_cntl_1;		/* 0x3f4 */
+	uint32_t cdb_cntl_2;		/* 0x3f8 */
+	uint32_t xm2clkpadctrl2;	/* 0x3fc */
+	uint32_t swizzle_rank0_byte_cfg;	/* 0x400 */
+	uint32_t swizzle_rank0_byte0;	/* 0x404 */
+	uint32_t swizzle_rank0_byte1;	/* 0x408 */
+	uint32_t swizzle_rank0_byte2;	/* 0x40c */
+	uint32_t swizzle_rank0_byte3;	/* 0x410 */
+	uint32_t swizzle_rank1_byte_cfg;	/* 0x414 */
+	uint32_t swizzle_rank1_byte0;	/* 0x418 */
+	uint32_t swizzle_rank1_byte1;	/* 0x41c */
+	uint32_t swizzle_rank1_byte2;	/* 0x420 */
+	uint32_t swizzle_rank1_byte3;	/* 0x424 */
+	uint32_t ca_training_start;	/* 0x428 */
+	uint32_t ca_training_busy;	/* 0x42c */
+	uint32_t ca_training_cfg;	/* 0x430 */
+	uint32_t ca_training_timing_cntl1;	/* 0x434 */
+	uint32_t ca_training_timing_cntl2;	/* 0x438 */
+	uint32_t ca_training_ca_lead_in;	/* 0x43c */
+	uint32_t ca_training_ca;	/* 0x440 */
+	uint32_t ca_training_ca_lead_out;	/* 0x444 */
+	uint32_t ca_training_result1;	/* 0x448 */
+	uint32_t ca_training_result2;	/* 0x44c */
+	uint32_t ca_training_result3;	/* 0x450 */
+	uint32_t ca_training_result4;	/* 0x454 */
+	uint32_t auto_cal_config2;	/* 0x458 */
+	uint32_t auto_cal_config3;	/* 0x45c */
+	uint32_t auto_cal_status2;	/* 0x460 */
+	uint32_t xm2cmdpadctrl3;	/* 0x464 */
+	uint32_t ibdly;			/* 0x468 */
+	uint32_t dll_xform_addr0;	/* 0x46c */
+	uint32_t dll_xform_addr1;	/* 0x470 */
+	uint32_t dll_xform_addr2;	/* 0x474 */
+	uint32_t dli_addr_trim;		/* 0x478 */
+	uint32_t dsr_vttgen_drv;	/* 0x47c */
+	uint32_t txdsrvttgen;		/* 0x480 */
+	uint32_t xm2cmdpadctrl4;	/* 0x484 */
+	uint32_t xm2cmdpadctrl5;	/* 0x488 */
+	uint32_t rsvd_0x48c[5];		/* 0x48c */
+
+	uint32_t dll_xform_dqs8;	/* 0x4a0 */
+	uint32_t dll_xform_dqs9;	/* 0x4a4 */
+	uint32_t dll_xform_dqs10;	/* 0x4a8 */
+	uint32_t dll_xform_dqs11;	/* 0x4ac */
+	uint32_t dll_xform_dqs12;	/* 0x4b0 */
+	uint32_t dll_xform_dqs13;	/* 0x4b4 */
+	uint32_t dll_xform_dqs14;	/* 0x4b8 */
+	uint32_t dll_xform_dqs15;	/* 0x4bc */
+	uint32_t dll_xform_quse8;	/* 0x4c0 */
+	uint32_t dll_xform_quse9;	/* 0x4c4 */
+	uint32_t dll_xform_quse10;	/* 0x4c8 */
+	uint32_t dll_xform_quse11;	/* 0x4cc */
+	uint32_t dll_xform_quse12;	/* 0x4d0 */
+	uint32_t dll_xform_quse13;	/* 0x4d4 */
+	uint32_t dll_xform_quse14;	/* 0x4d8 */
+	uint32_t dll_xform_quse15;	/* 0x4dc */
+	uint32_t dll_xform_dq4;		/* 0x4e0 */
+	uint32_t dll_xform_dq5;		/* 0x4e4 */
+	uint32_t dll_xform_dq6;		/* 0x4e8 */
+	uint32_t dll_xform_dq7;		/* 0x4ec */
+	uint32_t rsvd_0x4f0[12];		/* 0x4f0 */
+
+	uint32_t dli_trim_txdqs8;	/* 0x520 */
+	uint32_t dli_trim_txdqs9;	/* 0x524 */
+	uint32_t dli_trim_txdqs10;	/* 0x528 */
+	uint32_t dli_trim_txdqs11;	/* 0x52c */
+	uint32_t dli_trim_txdqs12;	/* 0x530 */
+	uint32_t dli_trim_txdqs13;	/* 0x534 */
+	uint32_t dli_trim_txdqs14;	/* 0x538 */
+	uint32_t dli_trim_txdqs15;	/* 0x53c */
+	uint32_t cdb_cntl_3;		/* 0x540 */
+	uint32_t xm2dqspadctrl5;	/* 0x544 */
+	uint32_t xm2dqspadctrl6;	/* 0x548 */
+	uint32_t xm2dqpadctrl3;		/* 0x54c */
+	uint32_t dll_xform_addr3;	/* 0x550 */
+	uint32_t dll_xform_addr4;	/* 0x554 */
+	uint32_t dll_xform_addr5;	/* 0x558 */
+	uint32_t rsvd_0x55c[1];		/* 0x55c */
+	uint32_t cfg_pipe;		/* 0x560 */
+	uint32_t qpop;			/* 0x564 */
+	uint32_t quse_width;		/* 0x568 */
+	uint32_t puterm_width;		/* 0x56c */
+	uint32_t bgbias_ctl0;		/* 0x570 */
+	uint32_t puterm_adj;		/* 0x574 */
+} __attribute__((packed));
+
+check_member(tegra_emc_regs, puterm_adj, 0x574);
+
+#endif /* __SOC_NVIDIA_TEGRA132_EMC_H__ */
diff --git a/src/soc/nvidia/tegra132/mc.h b/src/soc/nvidia/tegra132/mc.h
new file mode 100644
index 0000000000..a8815536be
--- /dev/null
+++ b/src/soc/nvidia/tegra132/mc.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2010 - 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_MC_H__
+#define __SOC_NVIDIA_TEGRA132_MC_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+// Memory Controller registers we need/care about
+
+struct tegra_mc_regs {
+	uint32_t rsvd_0x0[4];			/* 0x00 */
+	uint32_t smmu_config;			/* 0x10 */
+	uint32_t smmu_tlb_config;		/* 0x14 */
+	uint32_t smmu_ptc_config;		/* 0x18 */
+	uint32_t smmu_ptb_asid;			/* 0x1c */
+	uint32_t smmu_ptb_data;			/* 0x20 */
+	uint32_t rsvd_0x24[3];			/* 0x24 */
+	uint32_t smmu_tlb_flush;		/* 0x30 */
+	uint32_t smmu_ptc_flush;		/* 0x34 */
+	uint32_t rsvd_0x38[6];			/* 0x38 */
+	uint32_t emem_cfg;			/* 0x50 */
+	uint32_t emem_adr_cfg;			/* 0x54 */
+	uint32_t emem_adr_cfg_dev0;		/* 0x58 */
+	uint32_t emem_adr_cfg_dev1;		/* 0x5c */
+	uint32_t rsvd_0x60[1];			/* 0x60 */
+	uint32_t emem_adr_cfg_bank_mask_0;	/* 0x64 */
+	uint32_t emem_adr_cfg_bank_mask_1;	/* 0x68 */
+	uint32_t emem_adr_cfg_bank_mask_2;	/* 0x6c */
+	uint32_t rsvd_0x70[8];			/* 0x70 */
+	uint32_t emem_arb_cfg;			/* 0x90 */
+	uint32_t emem_arb_outstanding_req;	/* 0x94 */
+	uint32_t emem_arb_timing_rcd;		/* 0x98 */
+	uint32_t emem_arb_timing_rp;		/* 0x9c */
+	uint32_t emem_arb_timing_rc;		/* 0xa0 */
+	uint32_t emem_arb_timing_ras;		/* 0xa4 */
+	uint32_t emem_arb_timing_faw;		/* 0xa8 */
+	uint32_t emem_arb_timing_rrd;		/* 0xac */
+	uint32_t emem_arb_timing_rap2pre;	/* 0xb0 */
+	uint32_t emem_arb_timing_wap2pre;	/* 0xb4 */
+	uint32_t emem_arb_timing_r2r;		/* 0xb8 */
+	uint32_t emem_arb_timing_w2w;		/* 0xbc */
+	uint32_t emem_arb_timing_r2w;		/* 0xc0 */
+	uint32_t emem_arb_timing_w2r;		/* 0xc4 */
+	uint32_t rsvd_0xc8[2];			/* 0xc8 */
+	uint32_t emem_arb_da_turns;		/* 0xd0 */
+	uint32_t emem_arb_da_covers;		/* 0xd4 */
+	uint32_t emem_arb_misc0;		/* 0xd8 */
+	uint32_t emem_arb_misc1;		/* 0xdc */
+	uint32_t emem_arb_ring1_throttle;	/* 0xe0 */
+	uint32_t emem_arb_ring3_throttle;	/* 0xe4 */
+	uint32_t emem_arb_override;		/* 0xe8 */
+	uint32_t emem_arb_rsv;			/* 0xec */
+	uint32_t rsvd_0xf0[1];			/* 0xf0 */
+	uint32_t clken_override;		/* 0xf4 */
+	uint32_t timing_control_dbg;		/* 0xf8 */
+	uint32_t timing_control;		/* 0xfc */
+	uint32_t stat_control;			/* 0x100 */
+	uint32_t rsvd_0x104[65];		/* 0x104 */
+	uint32_t emem_arb_isochronous_0;	/* 0x208 */
+	uint32_t emem_arb_isochronous_1;	/* 0x20c */
+	uint32_t emem_arb_isochronous_2;	/* 0x210 */
+	uint32_t rsvd_0x214[38];		/* 0x214 */
+	uint32_t dis_extra_snap_levels;		/* 0x2ac */
+	uint32_t rsvd_0x2b0[90];		/* 0x2b0 */
+	uint32_t video_protect_vpr_override;	/* 0x418 */
+	uint32_t rsvd_0x41c[93];		/* 0x41c */
+	uint32_t video_protect_vpr_override1;	/* 0x590 */
+	uint32_t rsvd_0x594[29];		/* 0x594 */
+	uint32_t display_snap_ring;		/* 0x608 */
+	uint32_t rsvd_0x60c[15];		/* 0x60c */
+	uint32_t video_protect_bom;		/* 0x648 */
+	uint32_t video_protect_size_mb;		/* 0x64c */
+	uint32_t video_protect_reg_ctrl;	/* 0x650 */
+	uint32_t rsvd_0x654[4];			/* 0x654 */
+	uint32_t emem_cfg_access_ctrl;		/* 0x664 */
+	uint32_t rsvd_0x668[2];			/* 0x668 */
+	uint32_t sec_carveout_bom;		/* 0x670 */
+	uint32_t sec_carveout_size_mb;		/* 0x674 */
+	uint32_t sec_carveout_reg_ctrl;		/* 0x678 */
+	uint32_t rsvd_0x67c[187];		/* 0x67c */
+	uint32_t emem_arb_override_1;		/* 0x968 */
+	uint32_t rsvd_0x96c[3];			/* 0x96c */
+	uint32_t video_protect_bom_adr_hi;	/* 0x978 */
+	uint32_t rsvd_0x97c[2];			/* 0x97c */
+	uint32_t video_protect_gpu_override_0;	/* 0x984 */
+	uint32_t video_protect_gpu_override_1;	/* 0x988 */
+	uint32_t rsvd_0x98c[5];			/* 0x98c */
+	uint32_t mts_carveout_bom;		/* 0x9a0 */
+	uint32_t mts_carveout_size_mb;		/* 0x9a4 */
+	uint32_t mts_carveout_adr_hi;		/* 0x9a8 */
+	uint32_t mts_carveout_reg_ctrl;		/* 0x9ac */
+	uint32_t rsvd_0x9b0[4];			/* 0x9b0 */
+	uint32_t emem_bank_swizzle_cfg0;	/* 0x9c0 */
+	uint32_t emem_bank_swizzle_cfg1;	/* 0x9c4 */
+	uint32_t emem_bank_swizzle_cfg2;	/* 0x9c8 */
+	uint32_t emem_bank_swizzle_cfg3;	/* 0x9cc */
+	uint32_t rsvd_0x9d0[1];			/* 0x9d0 */
+	uint32_t sec_carveout_adr_hi;		/* 0x9d4 */
+};
+
+enum {
+	MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
+	MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
+
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
+
+	MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
+
+	MC_TIMING_CONTROL_TIMING_UPDATE = 1,
+};
+
+check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4);
+
+#endif	/* __SOC_NVIDIA_TEGRA132_MC_H__ */
diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c
new file mode 100644
index 0000000000..4e1f7ecfe8
--- /dev/null
+++ b/src/soc/nvidia/tegra132/sdram.c
@@ -0,0 +1,647 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <stdlib.h>
+
+#include "emc.h"
+#include "mc.h"
+#include "pmc.h"
+#include "sdram.h"
+
+static void sdram_patch(uintptr_t addr, uint32_t value)
+{
+	if (addr)
+		writel(value, (uint32_t*)addr);
+}
+
+static void writebits(uint32_t value, uint32_t *addr, uint32_t mask)
+{
+	clrsetbits_le32(addr, mask, (value & mask));
+}
+
+/* PMC must be configured before clock-enable and de-reset of MC/EMC. */
+static void sdram_configure_pmc(const struct sdram_params *param,
+				struct tegra_pmc_regs *regs)
+{
+	/* VDDP Select */
+	writel(param->PmcVddpSel, &regs->vddp_sel);
+	udelay(param->PmcVddpSelWait);
+
+	/* Set DDR pad voltage */
+	writebits(param->PmcDdrPwr, &regs->ddr_pwr, PMC_DDR_PWR_VAL_MASK);
+
+	/* Set package and DPD pad control */
+	writebits(param->PmcDdrCfg, &regs->ddr_cfg,
+		  (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK |
+		   PMC_DDR_CFG_XM0_RESET_TRI_MASK |
+		   PMC_DDR_CFG_XM0_RESET_DPDIO_MASK));
+
+	/* Turn on MEM IO Power */
+	writebits(param->PmcNoIoPower, &regs->no_iopower,
+		  (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK));
+
+	writel(param->PmcRegShort, &regs->reg_short);
+}
+
+static void sdram_start_clocks(const struct sdram_params *param)
+{
+	u32 is_same_freq = (param->McEmemArbMisc0 &
+			    MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0;
+
+	clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider,
+		    param->PllMSelectDiv2, param->PllMSetupControl,
+		    param->PllMPDLshiftPh45, param->PllMPDLshiftPh90,
+		    param->PllMPDLshiftPh135, param->PllMKVCO,
+		    param->PllMKCP, param->PllMStableTime,
+		    param->EmcClockSource, is_same_freq);
+}
+
+static void sdram_deassert_clock_enable_signal(const struct sdram_params *param,
+					       struct tegra_pmc_regs *regs)
+{
+	clrbits_le32(&regs->por_dpd_ctrl,
+		     PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK);
+	udelay(param->PmcPorDpdCtrlWait);
+}
+
+static void sdram_deassert_sel_dpd(const struct sdram_params *param,
+				   struct tegra_pmc_regs *regs)
+{
+	clrbits_le32(&regs->por_dpd_ctrl,
+		     (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK |
+		      PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK));
+	/*
+	 * Note NVIDIA recommended to always do 10us delay here and ignore
+	 * BCT.PmcPorDpdCtrlWait.
+	 * */
+	udelay(10);
+}
+
+static void sdram_set_swizzle(const struct sdram_params *param,
+			      struct tegra_emc_regs *regs)
+{
+	writel(param->EmcSwizzleRank0ByteCfg, &regs->swizzle_rank0_byte_cfg);
+	writel(param->EmcSwizzleRank0Byte0, &regs->swizzle_rank0_byte0);
+	writel(param->EmcSwizzleRank0Byte1, &regs->swizzle_rank0_byte1);
+	writel(param->EmcSwizzleRank0Byte2, &regs->swizzle_rank0_byte2);
+	writel(param->EmcSwizzleRank0Byte3, &regs->swizzle_rank0_byte3);
+	writel(param->EmcSwizzleRank1ByteCfg, &regs->swizzle_rank1_byte_cfg);
+	writel(param->EmcSwizzleRank1Byte0, &regs->swizzle_rank1_byte0);
+	writel(param->EmcSwizzleRank1Byte1, &regs->swizzle_rank1_byte1);
+	writel(param->EmcSwizzleRank1Byte2, &regs->swizzle_rank1_byte2);
+	writel(param->EmcSwizzleRank1Byte3, &regs->swizzle_rank1_byte3);
+}
+
+static void sdram_set_pad_controls(const struct sdram_params *param,
+				   struct tegra_emc_regs *regs)
+{
+	/* Program the pad controls */
+	writel(param->EmcXm2CmdPadCtrl, &regs->xm2cmdpadctrl);
+	writel(param->EmcXm2CmdPadCtrl2, &regs->xm2cmdpadctrl2);
+	writel(param->EmcXm2CmdPadCtrl3, &regs->xm2cmdpadctrl3);
+	writel(param->EmcXm2CmdPadCtrl4, &regs->xm2cmdpadctrl4);
+	writel(param->EmcXm2CmdPadCtrl5, &regs->xm2cmdpadctrl5);
+
+	writel(param->EmcXm2DqsPadCtrl, &regs->xm2dqspadctrl);
+	writel(param->EmcXm2DqsPadCtrl2, &regs->xm2dqspadctrl2);
+	writel(param->EmcXm2DqsPadCtrl3, &regs->xm2dqspadctrl3);
+	writel(param->EmcXm2DqsPadCtrl4, &regs->xm2dqspadctrl4);
+	writel(param->EmcXm2DqsPadCtrl5, &regs->xm2dqspadctrl5);
+	writel(param->EmcXm2DqsPadCtrl6, &regs->xm2dqspadctrl6);
+
+	writel(param->EmcXm2DqPadCtrl, &regs->xm2dqpadctrl);
+	writel(param->EmcXm2DqPadCtrl2, &regs->xm2dqpadctrl2);
+	writel(param->EmcXm2DqPadCtrl3, &regs->xm2dqpadctrl3);
+
+	writel(param->EmcXm2ClkPadCtrl, &regs->xm2clkpadctrl);
+	writel(param->EmcXm2ClkPadCtrl2, &regs->xm2clkpadctrl2);
+
+	writel(param->EmcXm2CompPadCtrl, &regs->xm2comppadctrl);
+
+	writel(param->EmcXm2VttGenPadCtrl, &regs->xm2vttgenpadctrl);
+	writel(param->EmcXm2VttGenPadCtrl2, &regs->xm2vttgenpadctrl2);
+	writel(param->EmcXm2VttGenPadCtrl3, &regs->xm2vttgenpadctrl3);
+
+	writel(param->EmcCttTermCtrl, &regs->ctt_term_ctrl);
+}
+
+static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs)
+{
+	writel(EMC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control);
+}
+
+static void sdram_init_mc(const struct sdram_params *param,
+			  struct tegra_mc_regs *regs)
+{
+	/* Initialize MC VPR settings */
+	writel(param->McDisplaySnapRing, &regs->display_snap_ring);
+	writel(param->McVideoProtectBom, &regs->video_protect_bom);
+	writel(param->McVideoProtectBomAdrHi, &regs->video_protect_bom_adr_hi);
+	writel(param->McVideoProtectSizeMb, &regs->video_protect_size_mb);
+	writel(param->McVideoProtectVprOverride,
+	       &regs->video_protect_vpr_override);
+	writel(param->McVideoProtectVprOverride1,
+	       &regs->video_protect_vpr_override1);
+	writel(param->McVideoProtectGpuOverride0,
+	       &regs->video_protect_gpu_override_0);
+	writel(param->McVideoProtectGpuOverride1,
+	       &regs->video_protect_gpu_override_1);
+
+	/* Program SDRAM geometry paarameters */
+	writel(param->McEmemAdrCfg, &regs->emem_adr_cfg);
+	writel(param->McEmemAdrCfgDev0, &regs->emem_adr_cfg_dev0);
+	writel(param->McEmemAdrCfgDev1, &regs->emem_adr_cfg_dev1);
+
+	/* Program bank swizzling */
+	writel(param->McEmemAdrCfgBankMask0, &regs->emem_bank_swizzle_cfg0);
+	writel(param->McEmemAdrCfgBankMask1, &regs->emem_bank_swizzle_cfg1);
+	writel(param->McEmemAdrCfgBankMask2, &regs->emem_bank_swizzle_cfg2);
+	writel(param->McEmemAdrCfgBankSwizzle3, &regs->emem_bank_swizzle_cfg3);
+
+	/* Program external memory aperature (base and size) */
+	writel(param->McEmemCfg, &regs->emem_cfg);
+
+	/* Program SEC carveout (base and size) */
+	writel(param->McSecCarveoutBom, &regs->sec_carveout_bom);
+	writel(param->McSecCarveoutAdrHi, &regs->sec_carveout_adr_hi);
+	writel(param->McSecCarveoutSizeMb, &regs->sec_carveout_size_mb);
+
+	/* Program MTS carveout (base and size) */
+	writel(param->McMtsCarveoutBom, &regs->mts_carveout_bom);
+	writel(param->McMtsCarveoutAdrHi, &regs->mts_carveout_adr_hi);
+	writel(param->McMtsCarveoutSizeMb, &regs->mts_carveout_size_mb);
+
+	/* Program the memory arbiter */
+	writel(param->McEmemArbCfg, &regs->emem_arb_cfg);
+	writel(param->McEmemArbOutstandingReq, &regs->emem_arb_outstanding_req);
+	writel(param->McEmemArbTimingRcd, &regs->emem_arb_timing_rcd);
+	writel(param->McEmemArbTimingRp, &regs->emem_arb_timing_rp);
+	writel(param->McEmemArbTimingRc, &regs->emem_arb_timing_rc);
+	writel(param->McEmemArbTimingRas, &regs->emem_arb_timing_ras);
+	writel(param->McEmemArbTimingFaw, &regs->emem_arb_timing_faw);
+	writel(param->McEmemArbTimingRrd, &regs->emem_arb_timing_rrd);
+	writel(param->McEmemArbTimingRap2Pre, &regs->emem_arb_timing_rap2pre);
+	writel(param->McEmemArbTimingWap2Pre, &regs->emem_arb_timing_wap2pre);
+	writel(param->McEmemArbTimingR2R, &regs->emem_arb_timing_r2r);
+	writel(param->McEmemArbTimingW2W, &regs->emem_arb_timing_w2w);
+	writel(param->McEmemArbTimingR2W, &regs->emem_arb_timing_r2w);
+	writel(param->McEmemArbTimingW2R, &regs->emem_arb_timing_w2r);
+	writel(param->McEmemArbDaTurns, &regs->emem_arb_da_turns);
+	writel(param->McEmemArbDaCovers, &regs->emem_arb_da_covers);
+	writel(param->McEmemArbMisc0, &regs->emem_arb_misc0);
+	writel(param->McEmemArbMisc1, &regs->emem_arb_misc1);
+	writel(param->McEmemArbRing1Throttle, &regs->emem_arb_ring1_throttle);
+	writel(param->McEmemArbOverride, &regs->emem_arb_override);
+	writel(param->McEmemArbOverride1, &regs->emem_arb_override_1);
+	writel(param->McEmemArbRsv, &regs->emem_arb_rsv);
+
+	/* Program extra snap levels for display client */
+	writel(param->McDisExtraSnapLevels, &regs->dis_extra_snap_levels);
+
+	/* Trigger MC timing update */
+	writel(MC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control);
+
+	/* Program second-level clock enable overrides */
+	writel(param->McClkenOverride, &regs->clken_override);
+
+	/* Program statistics gathering */
+	writel(param->McStatControl, &regs->stat_control);
+}
+
+static void sdram_init_emc(const struct sdram_params *param,
+			   struct tegra_emc_regs *regs)
+{
+	/* Program SDRAM geometry parameters */
+	writel(param->EmcAdrCfg, &regs->adr_cfg);
+
+	/* Program second-level clock enable overrides */
+	writel(param->EmcClkenOverride, &regs->clken_override);
+
+	/* Program EMC pad auto calibration */
+	writel(param->EmcAutoCalInterval, &regs->auto_cal_interval);
+	writel(param->EmcAutoCalConfig2, &regs->auto_cal_config2);
+	writel(param->EmcAutoCalConfig3, &regs->auto_cal_config3);
+	writel(param->EmcAutoCalConfig, &regs->auto_cal_config);
+	udelay(param->EmcAutoCalWait);
+}
+
+static void sdram_set_emc_timing(const struct sdram_params *param,
+				 struct tegra_emc_regs *regs)
+{
+	/* Program EMC timing configuration */
+	writel(param->EmcCfg2, &regs->cfg_2);
+	writel(param->EmcCfgPipe, &regs->cfg_pipe);
+	writel(param->EmcDbg, &regs->dbg);
+	writel(param->EmcCmdQ, &regs->cmdq);
+	writel(param->EmcMc2EmcQ, &regs->mc2emcq);
+	writel(param->EmcMrsWaitCnt, &regs->mrs_wait_cnt);
+	writel(param->EmcMrsWaitCnt2, &regs->mrs_wait_cnt2);
+	writel(param->EmcFbioCfg5, &regs->fbio_cfg5);
+	writel(param->EmcRc, &regs->rc);
+	writel(param->EmcRfc, &regs->rfc);
+	writel(param->EmcRfcSlr, &regs->rfc_slr);
+	writel(param->EmcRas, &regs->ras);
+	writel(param->EmcRp, &regs->rp);
+	writel(param->EmcR2r, &regs->r2r);
+	writel(param->EmcW2w, &regs->w2w);
+	writel(param->EmcR2w, &regs->r2w);
+	writel(param->EmcW2r, &regs->w2r);
+	writel(param->EmcR2p, &regs->r2p);
+	writel(param->EmcW2p, &regs->w2p);
+	writel(param->EmcRdRcd, &regs->rd_rcd);
+	writel(param->EmcWrRcd, &regs->wr_rcd);
+	writel(param->EmcRrd, &regs->rrd);
+	writel(param->EmcRext, &regs->rext);
+	writel(param->EmcWext, &regs->wext);
+	writel(param->EmcWdv, &regs->wdv);
+	writel(param->EmcWdvMask, &regs->wdv_mask);
+	writel(param->EmcQUse, &regs->quse);
+	writel(param->EmcQuseWidth, &regs->quse_width);
+	writel(param->EmcIbdly, &regs->ibdly);
+	writel(param->EmcEInput, &regs->einput);
+	writel(param->EmcEInputDuration, &regs->einput_duration);
+	writel(param->EmcPutermExtra, &regs->puterm_extra);
+	writel(param->EmcPutermWidth, &regs->puterm_width);
+	writel(param->EmcPutermAdj, &regs->puterm_adj);
+	writel(param->EmcCdbCntl1, &regs->cdb_cntl_1);
+	writel(param->EmcCdbCntl2, &regs->cdb_cntl_2);
+	writel(param->EmcCdbCntl3, &regs->cdb_cntl_3);
+	writel(param->EmcQRst, &regs->qrst);
+	writel(param->EmcQSafe, &regs->qsafe);
+	writel(param->EmcRdv, &regs->rdv);
+	writel(param->EmcRdvMask, &regs->rdv_mask);
+	writel(param->EmcQpop, &regs->qpop);
+	writel(param->EmcCtt, &regs->ctt);
+	writel(param->EmcCttDuration, &regs->ctt_duration);
+	writel(param->EmcRefresh, &regs->refresh);
+	writel(param->EmcBurstRefreshNum, &regs->burst_refresh_num);
+	writel(param->EmcPreRefreshReqCnt, &regs->pre_refresh_req_cnt);
+	writel(param->EmcPdEx2Wr, &regs->pdex2wr);
+	writel(param->EmcPdEx2Rd, &regs->pdex2rd);
+	writel(param->EmcPChg2Pden, &regs->pchg2pden);
+	writel(param->EmcAct2Pden, &regs->act2pden);
+	writel(param->EmcAr2Pden, &regs->ar2pden);
+	writel(param->EmcRw2Pden, &regs->rw2pden);
+	writel(param->EmcTxsr, &regs->txsr);
+	writel(param->EmcTxsrDll, &regs->txsrdll);
+	writel(param->EmcTcke, &regs->tcke);
+	writel(param->EmcTckesr, &regs->tckesr);
+	writel(param->EmcTpd, &regs->tpd);
+	writel(param->EmcTfaw, &regs->tfaw);
+	writel(param->EmcTrpab, &regs->trpab);
+	writel(param->EmcTClkStable, &regs->tclkstable);
+	writel(param->EmcTClkStop, &regs->tclkstop);
+	writel(param->EmcTRefBw, &regs->trefbw);
+	writel(param->EmcOdtWrite, &regs->odt_write);
+	writel(param->EmcOdtRead, &regs->odt_read);
+	writel(param->EmcFbioCfg6, &regs->fbio_cfg6);
+	writel(param->EmcCfgDigDll, &regs->cfg_dig_dll);
+	writel(param->EmcCfgDigDllPeriod, &regs->cfg_dig_dll_period);
+
+	/* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */
+	writel(param->EmcFbioSpare & 0xfffffffd, &regs->fbio_spare);
+
+	writel(param->EmcCfgRsv, &regs->cfg_rsv);
+	writel(param->EmcDllXformDqs0, &regs->dll_xform_dqs0);
+	writel(param->EmcDllXformDqs1, &regs->dll_xform_dqs1);
+	writel(param->EmcDllXformDqs2, &regs->dll_xform_dqs2);
+	writel(param->EmcDllXformDqs3, &regs->dll_xform_dqs3);
+	writel(param->EmcDllXformDqs4, &regs->dll_xform_dqs4);
+	writel(param->EmcDllXformDqs5, &regs->dll_xform_dqs5);
+	writel(param->EmcDllXformDqs6, &regs->dll_xform_dqs6);
+	writel(param->EmcDllXformDqs7, &regs->dll_xform_dqs7);
+	writel(param->EmcDllXformDqs8, &regs->dll_xform_dqs8);
+	writel(param->EmcDllXformDqs9, &regs->dll_xform_dqs9);
+	writel(param->EmcDllXformDqs10, &regs->dll_xform_dqs10);
+	writel(param->EmcDllXformDqs11, &regs->dll_xform_dqs11);
+	writel(param->EmcDllXformDqs12, &regs->dll_xform_dqs12);
+	writel(param->EmcDllXformDqs13, &regs->dll_xform_dqs13);
+	writel(param->EmcDllXformDqs14, &regs->dll_xform_dqs14);
+	writel(param->EmcDllXformDqs15, &regs->dll_xform_dqs15);
+	writel(param->EmcDllXformQUse0, &regs->dll_xform_quse0);
+	writel(param->EmcDllXformQUse1, &regs->dll_xform_quse1);
+	writel(param->EmcDllXformQUse2, &regs->dll_xform_quse2);
+	writel(param->EmcDllXformQUse3, &regs->dll_xform_quse3);
+	writel(param->EmcDllXformQUse4, &regs->dll_xform_quse4);
+	writel(param->EmcDllXformQUse5, &regs->dll_xform_quse5);
+	writel(param->EmcDllXformQUse6, &regs->dll_xform_quse6);
+	writel(param->EmcDllXformQUse7, &regs->dll_xform_quse7);
+	writel(param->EmcDllXformQUse8, &regs->dll_xform_quse8);
+	writel(param->EmcDllXformQUse9, &regs->dll_xform_quse9);
+	writel(param->EmcDllXformQUse10, &regs->dll_xform_quse10);
+	writel(param->EmcDllXformQUse11, &regs->dll_xform_quse11);
+	writel(param->EmcDllXformQUse12, &regs->dll_xform_quse12);
+	writel(param->EmcDllXformQUse13, &regs->dll_xform_quse13);
+	writel(param->EmcDllXformQUse14, &regs->dll_xform_quse14);
+	writel(param->EmcDllXformQUse15, &regs->dll_xform_quse15);
+	writel(param->EmcDllXformDq0, &regs->dll_xform_dq0);
+	writel(param->EmcDllXformDq1, &regs->dll_xform_dq1);
+	writel(param->EmcDllXformDq2, &regs->dll_xform_dq2);
+	writel(param->EmcDllXformDq3, &regs->dll_xform_dq3);
+	writel(param->EmcDllXformDq4, &regs->dll_xform_dq4);
+	writel(param->EmcDllXformDq5, &regs->dll_xform_dq5);
+	writel(param->EmcDllXformDq6, &regs->dll_xform_dq6);
+	writel(param->EmcDllXformDq7, &regs->dll_xform_dq7);
+	writel(param->EmcDllXformAddr0, &regs->dll_xform_addr0);
+	writel(param->EmcDllXformAddr1, &regs->dll_xform_addr1);
+	writel(param->EmcDllXformAddr2, &regs->dll_xform_addr2);
+	writel(param->EmcDllXformAddr3, &regs->dll_xform_addr3);
+	writel(param->EmcDllXformAddr4, &regs->dll_xform_addr4);
+	writel(param->EmcDllXformAddr5, &regs->dll_xform_addr5);
+	writel(param->EmcAcpdControl, &regs->acpd_control);
+	writel(param->EmcDsrVttgenDrv, &regs->dsr_vttgen_drv);
+	writel(param->EmcTxdsrvttgen, &regs->txdsrvttgen);
+	writel(param->EmcBgbiasCtl0, &regs->bgbias_ctl0);
+
+	/*
+	 * Set pipe bypass enable bits before sending any DRAM commands.
+	 * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured.
+	 */
+	writebits(param->EmcCfg, &regs->cfg,
+		  (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK |
+		   EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK |
+		   EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK));
+}
+
+static void sdram_patch_bootrom(const struct sdram_params *param,
+				struct tegra_mc_regs *regs)
+{
+	if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) {
+		uintptr_t addr = ((param->BootRomPatchControl &
+				  BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >>
+				  BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT);
+		addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2);
+		writel(param->BootRomPatchData, (uint32_t *)addr);
+		writel(1, &regs->timing_control);
+	}
+}
+
+static void sdram_set_dpd3(const struct sdram_params *param,
+			   struct tegra_pmc_regs *regs)
+{
+	/* Program DPD request */
+	writel(param->PmcIoDpd3Req, &regs->io_dpd3_req);
+	udelay(param->PmcIoDpd3ReqWait);
+}
+
+static void sdram_set_dli_trims(const struct sdram_params *param,
+				struct tegra_emc_regs *regs)
+{
+	/* Program DLI trims */
+	writel(param->EmcDliTrimTxDqs0, &regs->dli_trim_txdqs0);
+	writel(param->EmcDliTrimTxDqs1, &regs->dli_trim_txdqs1);
+	writel(param->EmcDliTrimTxDqs2, &regs->dli_trim_txdqs2);
+	writel(param->EmcDliTrimTxDqs3, &regs->dli_trim_txdqs3);
+	writel(param->EmcDliTrimTxDqs4, &regs->dli_trim_txdqs4);
+	writel(param->EmcDliTrimTxDqs5, &regs->dli_trim_txdqs5);
+	writel(param->EmcDliTrimTxDqs6, &regs->dli_trim_txdqs6);
+	writel(param->EmcDliTrimTxDqs7, &regs->dli_trim_txdqs7);
+	writel(param->EmcDliTrimTxDqs8, &regs->dli_trim_txdqs8);
+	writel(param->EmcDliTrimTxDqs9, &regs->dli_trim_txdqs9);
+	writel(param->EmcDliTrimTxDqs10, &regs->dli_trim_txdqs10);
+	writel(param->EmcDliTrimTxDqs11, &regs->dli_trim_txdqs11);
+	writel(param->EmcDliTrimTxDqs12, &regs->dli_trim_txdqs12);
+	writel(param->EmcDliTrimTxDqs13, &regs->dli_trim_txdqs13);
+	writel(param->EmcDliTrimTxDqs14, &regs->dli_trim_txdqs14);
+	writel(param->EmcDliTrimTxDqs15, &regs->dli_trim_txdqs15);
+
+	writel(param->EmcCaTrainingTimingCntl1,
+	       &regs->ca_training_timing_cntl1);
+	writel(param->EmcCaTrainingTimingCntl2,
+	       &regs->ca_training_timing_cntl2);
+
+	sdram_trigger_emc_timing_update(regs);
+	udelay(param->EmcTimingControlWait);
+}
+
+static void sdram_set_clock_enable_signal(const struct sdram_params *param,
+					  struct tegra_emc_regs *regs)
+{
+	volatile uint32_t dummy = 0;
+	clrbits_le32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
+				  EMC_PIN_CKE_MASK));
+	/*
+	 * Assert dummy read of PIN register to ensure above write to PIN
+	 * register went through. 200 is the recommended value by NVIDIA.
+	 */
+	dummy |= readl(&regs->pin);
+	udelay(200 + param->EmcPinExtraWait);
+
+	/* Deassert reset */
+	setbits_le32(&regs->pin, EMC_PIN_RESET_INACTIVE);
+	/*
+	 * Assert dummy read of PIN register to ensure above write to PIN
+	 * register went through. 200 is the recommended value by NVIDIA.
+	 */
+	dummy |= readl(&regs->pin);
+	udelay(500 + param->EmcPinExtraWait);
+
+	/* Enable clock enable signal */
+	setbits_le32(&regs->pin, EMC_PIN_CKE_NORMAL);
+	/*
+	 * Assert dummy read of PIN register to ensure above write to PIN
+	 * register went through. 200 is the recommended value by NVIDIA.
+	 */
+	dummy |= readl(&regs->pin);
+	udelay(param->EmcPinProgramWait);
+
+	if (!dummy) {
+		die("Failed to program EMC pin.");
+	}
+
+	/* Send NOP (trigger) */
+	writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) |
+		   (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)),
+		  &regs->nop,
+		  EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK);
+
+	/* Write mode registers */
+	writel(param->EmcEmrs2, &regs->emrs2);
+	writel(param->EmcEmrs3, &regs->emrs3);
+	writel(param->EmcEmrs, &regs->emrs);
+	writel(param->EmcMrs, &regs->mrs);
+
+	if (param->EmcExtraModeRegWriteEnable) {
+		writel(param->EmcMrwExtra, &regs->mrs);
+	}
+}
+
+static void sdram_init_zq_calibration(const struct sdram_params *param,
+				      struct tegra_emc_regs *regs)
+{
+	if ((param->EmcZcalWarmColdBootEnables &
+	     EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) {
+		/* Need to initialize ZCAL on coldboot. */
+		writel(param->EmcZcalInitDev0, &regs->zq_cal);
+		udelay(param->EmcZcalInitWait);
+
+		if ((param->EmcDevSelect & 2) == 0) {
+			writel(param->EmcZcalInitDev1, &regs->zq_cal);
+			udelay(param->EmcZcalInitWait);
+		}
+	} else {
+		udelay(param->EmcZcalInitWait);
+	}
+}
+
+static void sdram_set_zq_calibration(const struct sdram_params *param,
+				     struct tegra_emc_regs *regs)
+{
+	/* Start periodic ZQ calibration */
+	writel(param->EmcZcalInterval, &regs->zcal_interval);
+	writel(param->EmcZcalWaitCnt, &regs->zcal_wait_cnt);
+	writel(param->EmcZcalMrwCmd, &regs->zcal_mrw_cmd);
+}
+
+static void sdram_set_refresh(const struct sdram_params *param,
+			      struct tegra_emc_regs *regs)
+{
+	/* Insert burst refresh */
+	if (param->EmcExtraRefreshNum > 0) {
+		uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1;
+		writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED |
+			   (refresh_num << EMC_REF_NUM_SHIFT) |
+			   (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)),
+			  &regs->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK |
+				       EMC_REF_NUM_MASK |
+				       EMC_REF_DEV_SELECTN_MASK));
+	}
+
+	/* Enable refresh */
+	writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED),
+	       &regs->refctrl);
+
+	writel(param->EmcDynSelfRefControl, &regs->dyn_self_ref_control);
+	writel(param->EmcCfg, &regs->cfg);
+	writel(param->EmcSelDpdCtrl, &regs->sel_dpd_ctrl);
+
+	/* Write addr swizzle lock bit */
+	writel(param->EmcFbioSpare, &regs->fbio_spare);
+
+	/* Re-trigger timing to latch power saving functions */
+	sdram_trigger_emc_timing_update(regs);
+}
+
+static void sdram_enable_arbiter(const struct sdram_params *param)
+{
+	/* TODO(hungte) Move values here to standalone header file. */
+	uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0);
+	setbits_le32(AHB_ARBITRATION_XBAR_CTRL,
+		     param->AhbArbitrationXbarCtrlMemInitDone << 16);
+}
+
+static void sdram_lock_carveouts(const struct sdram_params *param,
+				 struct tegra_mc_regs *regs)
+{
+	/* Lock carveouts, and emem_cfg registers */
+	writel(param->McVideoProtectWriteAccess, &regs->video_protect_reg_ctrl);
+	writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED,
+	       &regs->emem_cfg_access_ctrl);
+	writel(param->McSecCarveoutProtectWriteAccess,
+	       &regs->sec_carveout_reg_ctrl);
+	writel(param->McMtsCarveoutRegCtrl, &regs->mts_carveout_reg_ctrl);
+}
+
+void sdram_init(const struct sdram_params *param)
+{
+	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
+	struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE;
+	struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE;
+
+	printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n",
+		param->MemoryType, clock_get_pll_input_khz() *
+		param->PllMFeedbackDivider / param->PllMInputDivider /
+		(1 + param->PllMSelectDiv2));
+	if (param->MemoryType != NvBootMemoryType_Ddr3)
+		die("Unsupported memory type!\n");
+
+	sdram_configure_pmc(param, pmc);
+	sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1);
+
+	sdram_start_clocks(param);
+	sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3);
+
+	sdram_deassert_sel_dpd(param, pmc);
+	sdram_set_swizzle(param, emc);
+	sdram_set_pad_controls(param, emc);
+	sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5);
+
+	sdram_trigger_emc_timing_update(emc);
+	sdram_init_mc(param, mc);
+	sdram_init_emc(param, emc);
+	sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7);
+
+	sdram_set_emc_timing(param, emc);
+	sdram_patch_bootrom(param, mc);
+	sdram_set_dpd3(param, pmc);
+	sdram_set_dli_trims(param, emc);
+	sdram_deassert_clock_enable_signal(param, pmc);
+	sdram_set_clock_enable_signal(param, emc);
+	sdram_init_zq_calibration(param, emc);
+	sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9);
+
+	sdram_set_zq_calibration(param, emc);
+	sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11);
+
+	sdram_trigger_emc_timing_update(emc);
+	sdram_set_refresh(param, emc);
+	sdram_enable_arbiter(param);
+	sdram_lock_carveouts(param, mc);
+
+	sdram_lp0_save_params(param);
+}
+
+uint32_t sdram_get_ram_code(void)
+{
+	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
+	return ((readl(&pmc->strapping_opt_a) &
+		 PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
+		PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
+}
+
+/* returns total amount of DRAM (in MB) from memory controller registers */
+int sdram_size_mb(void)
+{
+	struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE;
+	static int total_size = 0;
+
+	if (total_size)
+		return total_size;
+
+	/*
+	 * This obtains memory size from the External Memory Aperture
+	 * Configuration register. Nvidia confirmed that it is safe to assume
+	 * this value represents the total physical DRAM size.
+	 */
+	total_size = (read32(&mc->emem_cfg) >>
+			MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK;
+
+	printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size);
+	return total_size;
+}
+
+uintptr_t sdram_max_addressable_mb(void)
+{
+	return MIN((CONFIG_SYS_SDRAM_BASE/MiB) + sdram_size_mb(), 4096);
+}
diff --git a/src/soc/nvidia/tegra132/sdram.h b/src/soc/nvidia/tegra132/sdram.h
new file mode 100644
index 0000000000..ab6bf0fd18
--- /dev/null
+++ b/src/soc/nvidia/tegra132/sdram.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_H__
+#define __SOC_NVIDIA_TEGRA132_SDRAM_H__
+
+#include "sdram_param.h"
+
+uint32_t sdram_get_ram_code(void);
+void sdram_init(const struct sdram_params *param);
+int sdram_size_mb(void);
+uintptr_t sdram_max_addressable_mb(void);
+
+/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */
+void sdram_lp0_save_params(const struct sdram_params *sdram);
+
+#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_H__ */
diff --git a/src/soc/nvidia/tegra132/sdram_lp0.c b/src/soc/nvidia/tegra132/sdram_lp0.c
new file mode 100644
index 0000000000..2a88351656
--- /dev/null
+++ b/src/soc/nvidia/tegra132/sdram_lp0.c
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arch/cache.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <soc/addressmap.h>
+
+#include "clk_rst.h"
+#include "pmc.h"
+#include "sdram.h"
+
+/*
+ * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from
+ * the common BCT format and writes them into PMC scratch registers (where the
+ * BootROM expects them on LP0 resume). Since those store the same values in a
+ * different format, we follow a "translation table" taken from Nvidia's U-Boot
+ * implementation to shift bits into the right position.
+ *
+ * Contrary to U-Boot, we transform the same macros directly into hardcoded
+ * assignments (without any pesky function calls or volatile qualifiers) to give
+ * the compiler as much room for optimization as possible. For that reason, we
+ * also intentionally avoid <arch/io.h> read/write macros, under the assumption
+ * that PMC scratch register accesses should not have side effects and can be
+ * arbitrarily reordered. For the few accesses that do have side-effects, the
+ * code must contain explicit memory barriers.
+ */
+void sdram_lp0_save_params(const struct sdram_params *sdram)
+{
+	struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE;
+	struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+#define pack(src, src_bits, dst, dst_bits) { \
+	_Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \
+		(0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \
+	_Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \
+		(0 ? dst_bits), "src and dst byte range lengths differ" ); \
+	u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
+	dst &= ~(mask << (0 ? dst_bits)); \
+	dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \
+}
+
+#define s(param, src_bits, pmcreg, dst_bits) \
+	pack(sdram->param, src_bits, pmc->pmcreg, dst_bits)
+
+#define m(clkreg, src_bits, pmcreg, dst_bits) \
+	pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits)
+
+#define c(value, pmcreg, dst_bits) \
+	pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits)
+
+	s(EmcClockSource, 7:0, scratch6, 15:8);
+	s(EmcClockSource, 31:29, scratch6, 18:16);
+	s(EmcClockSource, 26:26, scratch6, 19:19);
+	s(EmcOdtWrite, 5:0, scratch6, 25:20);
+	s(EmcOdtWrite, 11:8, scratch6, 29:26);
+	s(EmcOdtWrite, 30:30, scratch6, 30:30);
+	s(EmcOdtWrite, 31:31, scratch6, 31:31);
+	s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20);
+	s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23);
+	s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26);
+	s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29);
+	s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20);
+	s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23);
+	s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26);
+	s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29);
+	s(EmcTxsrDll, 11:0, scratch9, 31:20);
+	c(0, scratch10, 31:0);
+	s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20);
+	s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26);
+	s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29);
+	s(EmcFbioSpare, 31:24, scratch11, 7:0);
+	s(EmcFbioSpare, 23:16, scratch11, 15:8);
+	s(EmcFbioSpare, 15:8, scratch11, 23:16);
+	s(EmcFbioSpare, 7:0, scratch11, 31:24);
+	s(EmcCfgRsv, 31:0, scratch12, 31:0);
+	s(EmcCdbCntl2, 31:0, scratch13, 31:0);
+	s(McEmemArbDaTurns, 31:0, scratch14, 31:0);
+	s(EmcCfgDigDll, 0:0, scratch17, 0:0);
+	s(EmcCfgDigDll, 25:2, scratch17, 24:1);
+	s(EmcCfgDigDll, 31:27, scratch17, 29:25);
+	s(EmcCdbCntl1, 29:0, scratch18, 29:0);
+	s(McEmemArbMisc0, 14:0, scratch19, 14:0);
+	s(McEmemArbMisc0, 30:16, scratch19, 29:15);
+	s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0);
+	s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5);
+	s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10);
+	s(EmcRrd, 3:0, scratch22, 31:28);
+	s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0);
+	s(EmcRext, 3:0, scratch23, 31:28);
+	s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0);
+	s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17);
+	s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22);
+	s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23);
+	s(EmcR2w, 4:0, scratch24, 31:27);
+	s(EmcCfg, 9:1, scratch25, 8:0);
+	s(EmcCfg, 26:16, scratch25, 19:9);
+	s(EmcCfg, 31:28, scratch25, 23:20);
+	s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24);
+	s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25);
+	s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26);
+	s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29);
+	s(EmcZcalInterval, 23:10, scratch26, 13:0);
+	s(EmcZcalInterval, 9:0, scratch26, 23:14);
+	s(EmcSelDpdCtrl, 5:2, scratch26, 27:24);
+	s(EmcSelDpdCtrl, 8:8, scratch26, 28:28);
+	s(EmcSelDpdCtrl, 18:16, scratch26, 31:29);
+	s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0);
+	s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23);
+	s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24);
+	s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26);
+	s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28);
+	s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30);
+	s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0);
+	s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6);
+	s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12);
+	s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17);
+	s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18);
+	s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23);
+	s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24);
+	s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26);
+	s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28);
+	s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30);
+	s(McEmemArbDaCovers, 23:0, scratch29, 23:0);
+	s(McEmemArbRsv, 7:0, scratch29, 31:24);
+	s(EmcAutoCalConfig, 4:0, scratch30, 4:0);
+	s(EmcAutoCalConfig, 12:8, scratch30, 9:5);
+	s(EmcAutoCalConfig, 18:16, scratch30, 12:10);
+	s(EmcAutoCalConfig, 25:20, scratch30, 18:13);
+	s(EmcAutoCalConfig, 31:28, scratch30, 22:19);
+	s(EmcRfc, 8:0, scratch30, 31:23);
+	s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0);
+	s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22);
+	s(EmcAr2Pden, 8:0, scratch31, 31:23);
+	s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0);
+	s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1);
+	s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4);
+	s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5);
+	s(EmcRfcSlr, 8:0, scratch32, 31:23);
+	s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0);
+	s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1);
+	s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2);
+	s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7);
+	s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12);
+	s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17);
+	s(EmcTxsr, 9:0, scratch33, 31:22);
+	s(McEmemArbCfg, 8:0, scratch40, 8:0);
+	s(McEmemArbCfg, 20:16, scratch40, 13:9);
+	s(McEmemArbCfg, 27:24, scratch40, 17:14);
+	s(McEmemArbCfg, 31:28, scratch40, 21:18);
+	s(EmcMc2EmcQ, 2:0, scratch40, 24:22);
+	s(EmcMc2EmcQ, 10:8, scratch40, 27:25);
+	s(EmcMc2EmcQ, 27:24, scratch40, 31:28);
+	s(EmcAutoCalInterval, 20:0, scratch42, 20:0);
+	s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21);
+	s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30);
+	s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0);
+	s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10);
+	s(EmcTxdsrvttgen, 11:0, scratch44, 31:20);
+	s(EmcMrsWaitCnt, 9:0, scratch45, 9:0);
+	s(EmcMrsWaitCnt, 25:16, scratch45, 19:10);
+	s(EmcCfgPipe, 1:0, scratch45, 21:20);
+	s(EmcCfgPipe, 9:4, scratch45, 27:22);
+	s(EmcCfgPipe, 15:12, scratch45, 31:28);
+	s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0);
+	s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5);
+	s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10);
+	s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15);
+	s(EmcZcalWaitCnt, 9:0, scratch46, 29:20);
+	s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0);
+	s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5);
+	s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10);
+	s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15);
+	s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20);
+	s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26);
+	s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0);
+	s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5);
+	s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10);
+	s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15);
+	s(EmcAutoCalConfig3, 4:0, scratch48, 24:20);
+	s(EmcAutoCalConfig3, 12:8, scratch48, 29:25);
+	s(EmcFbioCfg5, 1:0, scratch48, 31:30);
+	s(EmcDllXformQUse8, 4:0, scratch50, 4:0);
+	s(EmcDllXformQUse8, 22:8, scratch50, 19:5);
+	s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20);
+	s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25);
+	s(EmcFbioCfg5, 3:2, scratch50, 31:30);
+	s(EmcDllXformQUse9, 4:0, scratch51, 4:0);
+	s(EmcDllXformQUse9, 22:8, scratch51, 19:5);
+	s(EmcCttTermCtrl, 2:0, scratch51, 22:20);
+	s(EmcCttTermCtrl, 12:8, scratch51, 27:23);
+	s(EmcCttTermCtrl, 31:31, scratch51, 28:28);
+	s(EmcFbioCfg6, 2:0, scratch51, 31:29);
+	s(EmcDllXformQUse10, 4:0, scratch56, 4:0);
+	s(EmcDllXformQUse10, 22:8, scratch56, 19:5);
+	s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20);
+	s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28);
+	s(EmcPutermAdj, 1:0, scratch56, 30:29);
+	s(EmcPutermAdj, 7:7, scratch56, 31:31);
+	s(EmcDllXformQUse11, 4:0, scratch57, 4:0);
+	s(EmcDllXformQUse11, 22:8, scratch57, 19:5);
+	s(EmcWdv, 3:0, scratch57, 31:28);
+	s(EmcDllXformQUse12, 4:0, scratch58, 4:0);
+	s(EmcDllXformQUse12, 22:8, scratch58, 19:5);
+	s(EmcBurstRefreshNum, 3:0, scratch58, 31:28);
+	s(EmcDllXformQUse13, 4:0, scratch59, 4:0);
+	s(EmcDllXformQUse13, 22:8, scratch59, 19:5);
+	s(EmcWext, 3:0, scratch59, 31:28);
+	s(EmcDllXformQUse14, 4:0, scratch60, 4:0);
+	s(EmcDllXformQUse14, 22:8, scratch60, 19:5);
+	s(EmcClkenOverride, 3:1, scratch60, 30:28);
+	s(EmcClkenOverride, 6:6, scratch60, 31:31);
+	s(EmcDllXformQUse15, 4:0, scratch61, 4:0);
+	s(EmcDllXformQUse15, 22:8, scratch61, 19:5);
+	s(EmcR2r, 3:0, scratch61, 31:28);
+	s(EmcDllXformDq4, 4:0, scratch62, 4:0);
+	s(EmcDllXformDq4, 22:8, scratch62, 19:5);
+	s(EmcRc, 6:0, scratch62, 26:20);
+	s(EmcW2r, 4:0, scratch62, 31:27);
+	s(EmcDllXformDq5, 4:0, scratch63, 4:0);
+	s(EmcDllXformDq5, 22:8, scratch63, 19:5);
+	s(EmcTfaw, 6:0, scratch63, 26:20);
+	s(EmcR2p, 4:0, scratch63, 31:27);
+	s(EmcDllXformDq6, 4:0, scratch64, 4:0);
+	s(EmcDllXformDq6, 22:8, scratch64, 19:5);
+	s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20);
+	s(EmcQSafe, 4:0, scratch64, 31:27);
+	s(EmcDllXformDq7, 4:0, scratch65, 4:0);
+	s(EmcDllXformDq7, 22:8, scratch65, 19:5);
+	s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20);
+	s(EmcTClkStable, 4:0, scratch65, 31:27);
+	s(EmcAutoCalConfig2, 4:0, scratch66, 4:0);
+	s(EmcAutoCalConfig2, 12:8, scratch66, 9:5);
+	s(EmcAutoCalConfig2, 20:16, scratch66, 14:10);
+	s(EmcAutoCalConfig2, 28:24, scratch66, 19:15);
+	s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20);
+	s(EmcTClkStop, 4:0, scratch66, 31:27);
+	s(McEmemArbMisc1, 1:0, scratch67, 1:0);
+	s(McEmemArbMisc1, 12:4, scratch67, 10:2);
+	s(McEmemArbMisc1, 25:21, scratch67, 15:11);
+	s(McEmemArbMisc1, 31:28, scratch67, 19:16);
+	s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20);
+	s(EmcEInputDuration, 4:0, scratch67, 31:27);
+	s(EmcZcalMrwCmd, 7:0, scratch68, 7:0);
+	s(EmcZcalMrwCmd, 23:16, scratch68, 15:8);
+	s(EmcZcalMrwCmd, 31:30, scratch68, 17:16);
+	s(EmcTRefBw, 13:0, scratch68, 31:18);
+	s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0);
+	s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18);
+	s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25);
+	s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0);
+	s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18);
+	s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25);
+	s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0);
+	s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3);
+	s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6);
+	s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9);
+	s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12);
+	s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15);
+	s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18);
+	s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25);
+	s(EmcCdbCntl3, 17:0, scratch72, 17:0);
+	s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18);
+	s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25);
+	s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0);
+	s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3);
+	s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6);
+	s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9);
+	s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12);
+	s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15);
+	s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18);
+	s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25);
+	s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0);
+	s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3);
+	s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6);
+	s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9);
+	s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12);
+	s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15);
+	s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18);
+	s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25);
+	s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0);
+	s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3);
+	s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6);
+	s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9);
+	s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12);
+	s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15);
+	s(McEmemArbTimingRp, 6:0, scratch75, 24:18);
+	s(McEmemArbTimingRc, 6:0, scratch75, 31:25);
+	s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0);
+	s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3);
+	s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6);
+	s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9);
+	s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12);
+	s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15);
+	s(McEmemArbTimingFaw, 6:0, scratch76, 24:18);
+	s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25);
+	s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0);
+	s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3);
+	s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6);
+	s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9);
+	s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12);
+	s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15);
+	s(EmcRas, 5:0, scratch77, 23:18);
+	s(EmcRp, 5:0, scratch77, 29:24);
+	s(EmcCfg2, 9:8, scratch77, 31:30);
+	s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0);
+	s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3);
+	s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6);
+	s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9);
+	s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12);
+	s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15);
+	s(EmcW2p, 5:0, scratch78, 23:18);
+	s(EmcRdRcd, 5:0, scratch78, 29:24);
+	s(EmcCfg2, 27:26, scratch78, 31:30);
+	s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0);
+	s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3);
+	s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6);
+	s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9);
+	s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12);
+	s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15);
+	s(EmcWrRcd, 5:0, scratch79, 23:18);
+	s(EmcQUse, 5:0, scratch79, 29:24);
+	s(EmcFbioCfg5, 4:4, scratch79, 31:31);
+	s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0);
+	s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3);
+	s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6);
+	s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9);
+	s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12);
+	s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15);
+	s(EmcQRst, 5:0, scratch80, 23:18);
+	s(EmcRdv, 5:0, scratch80, 29:24);
+	s(EmcFbioCfg5, 6:5, scratch80, 31:30);
+	s(EmcDynSelfRefControl, 15:0, scratch81, 15:0);
+	s(EmcDynSelfRefControl, 31:31, scratch81, 16:16);
+	s(EmcPdEx2Wr, 5:0, scratch81, 22:17);
+	s(EmcPdEx2Rd, 5:0, scratch81, 28:23);
+	s(EmcRefresh, 5:0, scratch82, 5:0);
+	s(EmcRefresh, 15:6, scratch82, 15:6);
+	s(EmcCmdQ, 4:0, scratch82, 20:16);
+	s(EmcCmdQ, 10:8, scratch82, 23:21);
+	s(EmcCmdQ, 14:12, scratch82, 26:24);
+	s(EmcCmdQ, 28:24, scratch82, 31:27);
+	s(EmcAcpdControl, 15:0, scratch83, 15:0);
+	s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16);
+	s(EmcDllXformDqs0, 4:0, scratch84, 4:0);
+	s(EmcDllXformDqs0, 22:12, scratch84, 15:5);
+	s(EmcDllXformDqs1, 4:0, scratch84, 20:16);
+	s(EmcDllXformDqs1, 22:12, scratch84, 31:21);
+	s(EmcDllXformDqs2, 4:0, scratch85, 4:0);
+	s(EmcDllXformDqs2, 22:12, scratch85, 15:5);
+	s(EmcDllXformDqs3, 4:0, scratch85, 20:16);
+	s(EmcDllXformDqs3, 22:12, scratch85, 31:21);
+	s(EmcDllXformDqs4, 4:0, scratch86, 4:0);
+	s(EmcDllXformDqs4, 22:12, scratch86, 15:5);
+	s(EmcDllXformDqs5, 4:0, scratch86, 20:16);
+	s(EmcDllXformDqs5, 22:12, scratch86, 31:21);
+	s(EmcDllXformDqs6, 4:0, scratch87, 4:0);
+	s(EmcDllXformDqs6, 22:12, scratch87, 15:5);
+	s(EmcDllXformDqs7, 4:0, scratch87, 20:16);
+	s(EmcDllXformDqs7, 22:12, scratch87, 31:21);
+	s(EmcDllXformDqs8, 4:0, scratch88, 4:0);
+	s(EmcDllXformDqs8, 22:12, scratch88, 15:5);
+	s(EmcDllXformDqs9, 4:0, scratch88, 20:16);
+	s(EmcDllXformDqs9, 22:12, scratch88, 31:21);
+	s(EmcDllXformDqs10, 4:0, scratch89, 4:0);
+	s(EmcDllXformDqs10, 22:12, scratch89, 15:5);
+	s(EmcDllXformDqs11, 4:0, scratch89, 20:16);
+	s(EmcDllXformDqs11, 22:12, scratch89, 31:21);
+	s(EmcDllXformDqs12, 4:0, scratch90, 4:0);
+	s(EmcDllXformDqs12, 22:12, scratch90, 15:5);
+	s(EmcDllXformDqs13, 4:0, scratch90, 20:16);
+	s(EmcDllXformDqs13, 22:12, scratch90, 31:21);
+	s(EmcDllXformDqs14, 4:0, scratch91, 4:0);
+	s(EmcDllXformDqs14, 22:12, scratch91, 15:5);
+	s(EmcDllXformDqs15, 4:0, scratch91, 20:16);
+	s(EmcDllXformDqs15, 22:12, scratch91, 31:21);
+	s(EmcDllXformQUse0, 4:0, scratch92, 4:0);
+	s(EmcDllXformQUse0, 22:12, scratch92, 15:5);
+	s(EmcDllXformQUse1, 4:0, scratch92, 20:16);
+	s(EmcDllXformQUse1, 22:12, scratch92, 31:21);
+	s(EmcDllXformQUse2, 4:0, scratch93, 4:0);
+	s(EmcDllXformQUse2, 22:12, scratch93, 15:5);
+	s(EmcDllXformQUse3, 4:0, scratch93, 20:16);
+	s(EmcDllXformQUse3, 22:12, scratch93, 31:21);
+	s(EmcDllXformQUse4, 4:0, scratch94, 4:0);
+	s(EmcDllXformQUse4, 22:12, scratch94, 15:5);
+	s(EmcDllXformQUse5, 4:0, scratch94, 20:16);
+	s(EmcDllXformQUse5, 22:12, scratch94, 31:21);
+	s(EmcDllXformQUse6, 4:0, scratch95, 4:0);
+	s(EmcDllXformQUse6, 22:12, scratch95, 15:5);
+	s(EmcDllXformQUse7, 4:0, scratch95, 20:16);
+	s(EmcDllXformQUse7, 22:12, scratch95, 31:21);
+	s(EmcDllXformDq0, 4:0, scratch96, 4:0);
+	s(EmcDllXformDq0, 22:12, scratch96, 15:5);
+	s(EmcDllXformDq1, 4:0, scratch96, 20:16);
+	s(EmcDllXformDq1, 22:12, scratch96, 31:21);
+	s(EmcDllXformDq2, 4:0, scratch97, 4:0);
+	s(EmcDllXformDq2, 22:12, scratch97, 15:5);
+	s(EmcDllXformDq3, 4:0, scratch97, 20:16);
+	s(EmcDllXformDq3, 22:12, scratch97, 31:21);
+	s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0);
+	s(EmcDllXformAddr0, 4:0, scratch98, 20:16);
+	s(EmcDllXformAddr0, 22:12, scratch98, 31:21);
+	s(EmcDllXformAddr1, 4:0, scratch99, 4:0);
+	s(EmcDllXformAddr1, 22:12, scratch99, 15:5);
+	s(EmcDllXformAddr2, 4:0, scratch99, 20:16);
+	s(EmcDllXformAddr2, 22:12, scratch99, 31:21);
+	s(EmcDllXformAddr3, 4:0, scratch100, 4:0);
+	s(EmcDllXformAddr3, 22:12, scratch100, 15:5);
+	s(EmcDllXformAddr4, 4:0, scratch100, 20:16);
+	s(EmcDllXformAddr4, 22:12, scratch100, 31:21);
+	s(EmcDllXformAddr5, 4:0, scratch101, 4:0);
+	s(EmcDllXformAddr5, 22:12, scratch101, 15:5);
+	s(EmcPChg2Pden, 5:0, scratch102, 5:0);
+	s(EmcAct2Pden, 5:0, scratch102, 11:6);
+	s(EmcRw2Pden, 5:0, scratch102, 17:12);
+	s(EmcTcke, 5:0, scratch102, 23:18);
+	s(EmcTrpab, 5:0, scratch102, 29:24);
+	s(EmcFbioCfg5, 8:7, scratch102, 31:30);
+	s(EmcCtt, 5:0, scratch103, 5:0);
+	s(EmcEInput, 5:0, scratch103, 11:6);
+	s(EmcPutermExtra, 21:16, scratch103, 17:12);
+	s(EmcTckesr, 5:0, scratch103, 23:18);
+	s(EmcTpd, 5:0, scratch103, 29:24);
+	s(EmcFbioCfg5, 10:9, scratch103, 31:30);
+	s(EmcRdvMask, 5:0, scratch104, 5:0);
+	s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6);
+	s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7);
+	s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8);
+	s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9);
+	s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10);
+	s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11);
+	s(EmcQpop, 5:0, scratch104, 17:12);
+	s(McEmemArbTimingRcd, 5:0, scratch104, 23:18);
+	s(McEmemArbTimingRas, 5:0, scratch104, 29:24);
+	s(EmcFbioCfg5, 12:11, scratch104, 31:30);
+	s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0);
+	s(McEmemArbTimingR2W, 5:0, scratch105, 11:6);
+	s(McEmemArbTimingW2R, 5:0, scratch105, 17:12);
+	s(EmcIbdly, 4:0, scratch105, 22:18);
+	s(McEmemArbTimingR2R, 4:0, scratch105, 27:23);
+	s(EmcW2w, 3:0, scratch105, 31:28);
+	s(McEmemArbTimingW2W, 4:0, scratch106, 4:0);
+	s(McEmemArbOverride, 27:27, scratch106, 5:5);
+	s(McEmemArbOverride, 26:26, scratch106, 6:6);
+	s(McEmemArbOverride, 16:16, scratch106, 7:7);
+	s(McEmemArbOverride, 10:10, scratch106, 8:8);
+	s(McEmemArbOverride, 4:4, scratch106, 9:9);
+	s(EmcWdvMask, 3:0, scratch106, 13:10);
+	s(EmcCttDuration, 3:0, scratch106, 17:14);
+	s(EmcQuseWidth, 3:0, scratch106, 21:18);
+	s(EmcPutermWidth, 3:0, scratch106, 25:22);
+	s(EmcBgbiasCtl0, 3:0, scratch106, 29:26);
+	s(EmcFbioCfg5, 25:24, scratch106, 31:30);
+	s(McEmemArbTimingRrd, 3:0, scratch107, 3:0);
+	s(EmcFbioCfg5, 23:20, scratch107, 10:7);
+	s(EmcFbioCfg5, 15:13, scratch107, 13:11);
+	s(EmcCfg2, 5:3, scratch107, 16:14);
+	s(EmcFbioCfg5, 26:26, scratch107, 17:17);
+	s(EmcFbioCfg5, 28:28, scratch107, 18:18);
+	s(EmcCfg2, 2:0, scratch107, 21:19);
+	s(EmcCfg2, 7:6, scratch107, 23:22);
+	s(EmcCfg2, 15:10, scratch107, 29:24);
+	s(EmcCfg2, 23:22, scratch107, 31:30);
+	s(EmcCfg2, 25:24, scratch108, 1:0);
+	s(EmcCfg2, 31:28, scratch108, 5:2);
+	s(BootRomPatchData, 31:0, scratch15, 31:0);
+	s(BootRomPatchControl, 31:0, scratch16, 31:0);
+	s(EmcDevSelect, 1:0, scratch17, 31:30);
+	s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30);
+	s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30);
+	s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30);
+	s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31);
+	s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30);
+	s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31);
+	s(EmcTimingControlWait, 7:0, scratch57, 27:20);
+	s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20);
+	s(EmcAutoCalWait, 7:0, scratch59, 27:20);
+	s(WarmBootWait, 7:0, scratch60, 27:20);
+	s(EmcPinProgramWait, 7:0, scratch61, 27:20);
+	s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30);
+	s(EmcExtraRefreshNum, 2:0, scratch81, 31:29);
+	s(SwizzleRankByteEncode, 15:0, scratch101, 31:16);
+	s(MemoryType, 2:0, scratch107, 6:4);
+
+	switch (sdram->MemoryType) {
+	case NvBootMemoryType_LpDdr2:
+		s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0);
+		s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8);
+		s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16);
+		s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24);
+		s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0);
+		s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2);
+		s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4);
+		s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6);
+		s(EmcMrw1, 7:0, scratch7, 7:0);
+		s(EmcMrw1, 23:16, scratch7, 15:8);
+		s(EmcMrw1, 27:26, scratch7, 17:16);
+		s(EmcMrw1, 31:30, scratch7, 19:18);
+		s(EmcMrw2, 7:0, scratch8, 7:0);
+		s(EmcMrw2, 23:16, scratch8, 15:8);
+		s(EmcMrw2, 27:26, scratch8, 17:16);
+		s(EmcMrw2, 31:30, scratch8, 19:18);
+		s(EmcMrw3, 7:0, scratch9, 7:0);
+		s(EmcMrw3, 23:16, scratch9, 15:8);
+		s(EmcMrw3, 27:26, scratch9, 17:16);
+		s(EmcMrw3, 31:30, scratch9, 19:18);
+		s(EmcMrw4, 7:0, scratch10, 7:0);
+		s(EmcMrw4, 23:16, scratch10, 15:8);
+		s(EmcMrw4, 27:26, scratch10, 17:16);
+		s(EmcMrw4, 31:30, scratch10, 19:18);
+		break;
+	case NvBootMemoryType_Ddr3:
+		s(EmcMrs, 13:0, scratch5, 13:0);
+		s(EmcEmrs, 13:0, scratch5, 27:14);
+		s(EmcMrs, 21:20, scratch5, 29:28);
+		s(EmcMrs, 31:30, scratch5, 31:30);
+		s(EmcEmrs2, 13:0, scratch7, 13:0);
+		s(EmcEmrs, 21:20, scratch7, 15:14);
+		s(EmcEmrs, 31:30, scratch7, 17:16);
+		s(EmcEmrs2, 21:20, scratch7, 19:18);
+		s(EmcEmrs3, 13:0, scratch8, 13:0);
+		s(EmcEmrs2, 31:30, scratch8, 15:14);
+		s(EmcEmrs3, 21:20, scratch8, 17:16);
+		s(EmcEmrs3, 31:30, scratch8, 19:18);
+		s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0);
+		s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14);
+		s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16);
+		s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18);
+		s(EmcMrs, 27:26, scratch10, 1:0);
+		s(EmcEmrs, 27:26, scratch10, 3:2);
+		s(EmcEmrs2, 27:26, scratch10, 5:4);
+		s(EmcEmrs3, 27:26, scratch10, 7:6);
+		s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8);
+		s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9);
+		s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10);
+		s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11);
+		c(0, scratch116, 31:0);
+		c(0, scratch117, 31:0);
+		break;
+	default:
+		printk(BIOS_CRIT, "ERROR: %s() unrecognized MemoryType %d!\n",
+		       __func__, sdram->MemoryType);
+	}
+
+	s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0);
+	s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0);
+	s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4);
+	s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10);
+	s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20);
+	s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21);
+	s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24);
+	s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28);
+	s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30);
+	s(EmcAdrCfg, 0:0, secure_scratch9, 31:31);
+	s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0);
+	s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16);
+	s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0);
+	s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16);
+	s(McEmemCfg, 13:0, secure_scratch12, 13:0);
+	s(McEmemCfg, 31:31, secure_scratch12, 14:14);
+	s(McVideoProtectBom, 31:20, secure_scratch12, 26:15);
+	s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27);
+	s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29);
+	s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30);
+	s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0);
+	s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12);
+	s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24);
+	s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27);
+	s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29);
+	s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31);
+	s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0);
+	s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12);
+	s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24);
+	s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26);
+	s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27);
+	s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0);
+	s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12);
+	s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15);
+	s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17);
+	s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21);
+	s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24);
+	s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26);
+
+	c(0x1555555, sec_disable2, 25:0);
+	c(0xff, sec_disable, 19:12);
+
+	c(0, scratch2, 31:0);
+	m(pllm_base, 15:0, scratch2, 15:0);
+	m(pllm_base, 20:20, scratch2, 16:16);
+	m(pllm_misc2, 2:0, scratch2, 19:17);
+	c(0, scratch35, 31:0);
+	m(pllm_misc1, 23:0, scratch35, 23:0);
+	m(pllm_misc1, 30:28, scratch35, 30:28);
+	c(0, scratch3, 31:0);
+	s(PllMInputDivider, 7:0, scratch3, 7:0);
+	c(0x3e, scratch3, 15:8);
+	c(0, scratch3, 19:16);
+	s(PllMKVCO, 0:0, scratch3, 20:20);
+	s(PllMKCP, 1:0, scratch3, 22:21);
+	c(0, scratch36, 31:0);
+	s(PllMSetupControl, 23:0, scratch36, 23:0);
+	c(0, scratch4, 31:0);
+	s(PllMStableTime, 9:0, scratch4, 9:0);
+	s(PllMStableTime, 9:0, scratch4, 19:10);
+
+	s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27);
+	s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26);
+	s(PllMKCP, 1:0, pllm_wb0_override2, 25:24);
+	s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0);
+	s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8);
+	s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0);
+
+	c(3, pllp_wb0_override, 12:11);
+}
diff --git a/src/soc/nvidia/tegra132/sdram_param.h b/src/soc/nvidia/tegra132/sdram_param.h
new file mode 100644
index 0000000000..7688930c9a
--- /dev/null
+++ b/src/soc/nvidia/tegra132/sdram_param.h
@@ -0,0 +1,821 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+/**
+ * Defines the SDRAM parameter structure.
+ *
+ * Note that PLLM is used by EMC. The field names are in camel case to ease
+ * directly converting BCT config files (*.cfg) into C structure.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__
+#define __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+enum {
+	/* Specifies the memory type to be undefined */
+	NvBootMemoryType_None = 0,
+
+	/* Specifies the memory type to be DDR SDRAM */
+	NvBootMemoryType_Ddr = 0,
+
+	/* Specifies the memory type to be LPDDR SDRAM */
+	NvBootMemoryType_LpDdr = 0,
+
+	/* Specifies the memory type to be DDR2 SDRAM */
+	NvBootMemoryType_Ddr2 = 0,
+
+	/* Specifies the memory type to be LPDDR2 SDRAM */
+	NvBootMemoryType_LpDdr2,
+
+	/* Specifies the memory type to be DDR3 SDRAM */
+	NvBootMemoryType_Ddr3,
+
+	NvBootMemoryType_Num,
+
+	/* Specifies an entry in the ram_code table that's not in use */
+	NvBootMemoryType_Unused = 0X7FFFFFF,
+};
+
+enum {
+	BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31,
+	BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0,
+	BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0,
+	BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000,
+
+	EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0,
+};
+
+/**
+ * Defines the SDRAM parameter structure
+ */
+struct sdram_params {
+
+	/* Specifies the type of memory device */
+	uint32_t MemoryType;
+
+	/* MC/EMC clock source configuration */
+
+	/* Specifies the M value for PllM */
+	uint32_t PllMInputDivider;
+	/* Specifies the N value for PllM */
+	uint32_t PllMFeedbackDivider;
+	/* Specifies the time to wait for PLLM to lock (in microseconds) */
+	uint32_t PllMStableTime;
+	/* Specifies misc. control bits */
+	uint32_t PllMSetupControl;
+	/* Enables the Div by 2 */
+	uint32_t PllMSelectDiv2;
+	/* Powers down VCO output Level shifter */
+	uint32_t PllMPDLshiftPh45;
+	/* Powers down VCO output Level shifter */
+	uint32_t PllMPDLshiftPh90;
+	/* Powers down VCO output Level shifter */
+	uint32_t PllMPDLshiftPh135;
+	/* Specifies value for Charge Pump Gain Control */
+	uint32_t PllMKCP;
+	/* Specifies VCO gain */
+	uint32_t PllMKVCO;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare0;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare1;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare2;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare3;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare4;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare5;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare6;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare7;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare8;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare9;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare10;
+	/* Spare BCT param */
+	uint32_t EmcBctSpare11;
+	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
+	uint32_t EmcClockSource;
+
+	/* Auto-calibration of EMC pads */
+
+	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
+	uint32_t EmcAutoCalInterval;
+	/*
+	 * Specifies the value for EMC_AUTO_CAL_CONFIG
+	 * Note: Trigger bits are set by the SDRAM code.
+	 */
+	uint32_t EmcAutoCalConfig;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
+	uint32_t EmcAutoCalConfig2;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
+	uint32_t EmcAutoCalConfig3;
+
+	/*
+	 * Specifies the time for the calibration
+	 * to stabilize (in microseconds)
+	 */
+	uint32_t EmcAutoCalWait;
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	uint32_t EmcAdrCfg;
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	uint32_t EmcPinProgramWait;
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	uint32_t EmcPinExtraWait;
+	/*
+	 * Specifies the extra delay after the first writing
+	 * of EMC_TIMING_CONTROL
+	 */
+	uint32_t EmcTimingControlWait;
+
+	/* Timing parameters required for the SDRAM */
+
+	/* Specifies the value for EMC_RC */
+	uint32_t EmcRc;
+	/* Specifies the value for EMC_RFC */
+	uint32_t EmcRfc;
+	/* Specifies the value for EMC_RFC_SLR */
+	uint32_t EmcRfcSlr;
+	/* Specifies the value for EMC_RAS */
+	uint32_t EmcRas;
+	/* Specifies the value for EMC_RP */
+	uint32_t EmcRp;
+	/* Specifies the value for EMC_R2R */
+	uint32_t EmcR2r;
+	/* Specifies the value for EMC_W2W */
+	uint32_t EmcW2w;
+	/* Specifies the value for EMC_R2W */
+	uint32_t EmcR2w;
+	/* Specifies the value for EMC_W2R */
+	uint32_t EmcW2r;
+	/* Specifies the value for EMC_R2P */
+	uint32_t EmcR2p;
+	/* Specifies the value for EMC_W2P */
+	uint32_t EmcW2p;
+	/* Specifies the value for EMC_RD_RCD */
+	uint32_t EmcRdRcd;
+	/* Specifies the value for EMC_WR_RCD */
+	uint32_t EmcWrRcd;
+	/* Specifies the value for EMC_RRD */
+	uint32_t EmcRrd;
+	/* Specifies the value for EMC_REXT */
+	uint32_t EmcRext;
+	/* Specifies the value for EMC_WEXT */
+	uint32_t EmcWext;
+	/* Specifies the value for EMC_WDV */
+	uint32_t EmcWdv;
+	/* Specifies the value for EMC_WDV_MASK */
+	uint32_t EmcWdvMask;
+	/* Specifies the value for EMC_QUSE */
+	uint32_t EmcQUse;
+	/* Specifies the value for EMC_QUSE_WIDTH */
+	uint32_t EmcQuseWidth;
+	/* Specifies the value for EMC_IBDLY */
+	uint32_t EmcIbdly;
+	/* Specifies the value for EMC_EINPUT */
+	uint32_t EmcEInput;
+	/* Specifies the value for EMC_EINPUT_DURATION */
+	uint32_t EmcEInputDuration;
+	/* Specifies the value for EMC_PUTERM_EXTRA */
+	uint32_t EmcPutermExtra;
+	/* Specifies the value for EMC_PUTERM_WIDTH */
+	uint32_t EmcPutermWidth;
+	/* Specifies the value for EMC_PUTERM_ADJ */
+	uint32_t EmcPutermAdj;
+	/* Specifies the value for EMC_CDB_CNTL_1 */
+	uint32_t EmcCdbCntl1;
+	/* Specifies the value for EMC_CDB_CNTL_2 */
+	uint32_t EmcCdbCntl2;
+	/* Specifies the value for EMC_CDB_CNTL_3 */
+	uint32_t EmcCdbCntl3;
+	/* Specifies the value for EMC_QRST */
+	uint32_t EmcQRst;
+	/* Specifies the value for EMC_QSAFE */
+	uint32_t EmcQSafe;
+	/* Specifies the value for EMC_RDV */
+	uint32_t EmcRdv;
+	/* Specifies the value for EMC_RDV_MASK */
+	uint32_t EmcRdvMask;
+	/* Specifies the value for EMC_QPOP */
+	uint32_t EmcQpop;
+	/* Specifies the value for EMC_CTT */
+	uint32_t EmcCtt;
+	/* Specifies the value for EMC_CTT_DURATION */
+	uint32_t EmcCttDuration;
+	/* Specifies the value for EMC_REFRESH */
+	uint32_t EmcRefresh;
+	/* Specifies the value for EMC_BURST_REFRESH_NUM */
+	uint32_t EmcBurstRefreshNum;
+	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
+	uint32_t EmcPreRefreshReqCnt;
+	/* Specifies the value for EMC_PDEX2WR */
+	uint32_t EmcPdEx2Wr;
+	/* Specifies the value for EMC_PDEX2RD */
+	uint32_t EmcPdEx2Rd;
+	/* Specifies the value for EMC_PCHG2PDEN */
+	uint32_t EmcPChg2Pden;
+	/* Specifies the value for EMC_ACT2PDEN */
+	uint32_t EmcAct2Pden;
+	/* Specifies the value for EMC_AR2PDEN */
+	uint32_t EmcAr2Pden;
+	/* Specifies the value for EMC_RW2PDEN */
+	uint32_t EmcRw2Pden;
+	/* Specifies the value for EMC_TXSR */
+	uint32_t EmcTxsr;
+	/* Specifies the value for EMC_TXSRDLL */
+	uint32_t EmcTxsrDll;
+	/* Specifies the value for EMC_TCKE */
+	uint32_t EmcTcke;
+	/* Specifies the value for EMC_TCKESR */
+	uint32_t EmcTckesr;
+	/* Specifies the value for EMC_TPD */
+	uint32_t EmcTpd;
+	/* Specifies the value for EMC_TFAW */
+	uint32_t EmcTfaw;
+	/* Specifies the value for EMC_TRPAB */
+	uint32_t EmcTrpab;
+	/* Specifies the value for EMC_TCLKSTABLE */
+	uint32_t EmcTClkStable;
+	/* Specifies the value for EMC_TCLKSTOP */
+	uint32_t EmcTClkStop;
+	/* Specifies the value for EMC_TREFBW */
+	uint32_t EmcTRefBw;
+
+	/* FBIO configuration values */
+
+	/* Specifies the value for EMC_FBIO_CFG5 */
+	uint32_t EmcFbioCfg5;
+	/* Specifies the value for EMC_FBIO_CFG6 */
+	uint32_t EmcFbioCfg6;
+	/* Specifies the value for EMC_FBIO_SPARE */
+	uint32_t EmcFbioSpare;
+
+	/* Specifies the value for EMC_CFG_RSV */
+	uint32_t EmcCfgRsv;
+
+	/* MRS command values */
+
+	/* Specifies the value for EMC_MRS */
+	uint32_t EmcMrs;
+	/* Specifies the MP0 command to initialize mode registers */
+	uint32_t EmcEmrs;
+	/* Specifies the MP2 command to initialize mode registers */
+	uint32_t EmcEmrs2;
+	/* Specifies the MP3 command to initialize mode registers */
+	uint32_t EmcEmrs3;
+	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
+	uint32_t EmcMrw1;
+	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
+	uint32_t EmcMrw2;
+	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
+	uint32_t EmcMrw3;
+	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
+	uint32_t EmcMrw4;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at cold boot
+	 */
+	uint32_t EmcMrwExtra;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at warm boot
+	 */
+	uint32_t EmcWarmBootMrwExtra;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * warm boot
+	 */
+	uint32_t EmcWarmBootExtraModeRegWriteEnable;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * cold boot
+	 */
+	uint32_t EmcExtraModeRegWriteEnable;
+
+	/* Specifies the EMC_MRW reset command value */
+	uint32_t EmcMrwResetCommand;
+	/* Specifies the EMC Reset wait time (in microseconds) */
+	uint32_t EmcMrwResetNInitWait;
+	/* Specifies the value for EMC_MRS_WAIT_CNT */
+	uint32_t EmcMrsWaitCnt;
+	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
+	uint32_t EmcMrsWaitCnt2;
+
+	/* EMC miscellaneous configurations */
+
+	/* Specifies the value for EMC_CFG */
+	uint32_t EmcCfg;
+	/* Specifies the value for EMC_CFG_2 */
+	uint32_t EmcCfg2;
+	/* Specifies the pipe bypass controls */
+	uint32_t EmcCfgPipe;
+	/* Specifies the value for EMC_DBG */
+	uint32_t EmcDbg;
+	/* Specifies the value for EMC_CMDQ */
+	uint32_t EmcCmdQ;
+	/* Specifies the value for EMC_MC2EMCQ */
+	uint32_t EmcMc2EmcQ;
+	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
+	uint32_t EmcDynSelfRefControl;
+
+	/* Specifies the value for MEM_INIT_DONE */
+	uint32_t AhbArbitrationXbarCtrlMemInitDone;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL */
+	uint32_t EmcCfgDigDll;
+	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
+	uint32_t EmcCfgDigDllPeriod;
+	/* Specifies the value of *DEV_SELECTN of various EMC registers */
+	uint32_t EmcDevSelect;
+
+	/* Specifies the value for EMC_SEL_DPD_CTRL */
+	uint32_t EmcSelDpdCtrl;
+
+	/* Pads trimmer delays */
+
+	/* Specifies the value for EMC_DLL_XFORM_DQS0 */
+	uint32_t EmcDllXformDqs0;
+	/* Specifies the value for EMC_DLL_XFORM_DQS1 */
+	uint32_t EmcDllXformDqs1;
+	/* Specifies the value for EMC_DLL_XFORM_DQS2 */
+	uint32_t EmcDllXformDqs2;
+	/* Specifies the value for EMC_DLL_XFORM_DQS3 */
+	uint32_t EmcDllXformDqs3;
+	/* Specifies the value for EMC_DLL_XFORM_DQS4 */
+	uint32_t EmcDllXformDqs4;
+	/* Specifies the value for EMC_DLL_XFORM_DQS5 */
+	uint32_t EmcDllXformDqs5;
+	/* Specifies the value for EMC_DLL_XFORM_DQS6 */
+	uint32_t EmcDllXformDqs6;
+	/* Specifies the value for EMC_DLL_XFORM_DQS7 */
+	uint32_t EmcDllXformDqs7;
+	/* Specifies the value for EMC_DLL_XFORM_DQS8 */
+	uint32_t EmcDllXformDqs8;
+	/* Specifies the value for EMC_DLL_XFORM_DQS9 */
+	uint32_t EmcDllXformDqs9;
+	/* Specifies the value for EMC_DLL_XFORM_DQS10 */
+	uint32_t EmcDllXformDqs10;
+	/* Specifies the value for EMC_DLL_XFORM_DQS11 */
+	uint32_t EmcDllXformDqs11;
+	/* Specifies the value for EMC_DLL_XFORM_DQS12 */
+	uint32_t EmcDllXformDqs12;
+	/* Specifies the value for EMC_DLL_XFORM_DQS13 */
+	uint32_t EmcDllXformDqs13;
+	/* Specifies the value for EMC_DLL_XFORM_DQS14 */
+	uint32_t EmcDllXformDqs14;
+	/* Specifies the value for EMC_DLL_XFORM_DQS15 */
+	uint32_t EmcDllXformDqs15;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE0 */
+	uint32_t EmcDllXformQUse0;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE1 */
+	uint32_t EmcDllXformQUse1;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE2 */
+	uint32_t EmcDllXformQUse2;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE3 */
+	uint32_t EmcDllXformQUse3;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE4 */
+	uint32_t EmcDllXformQUse4;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE5 */
+	uint32_t EmcDllXformQUse5;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE6 */
+	uint32_t EmcDllXformQUse6;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE7 */
+	uint32_t EmcDllXformQUse7;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR0 */
+	uint32_t EmcDllXformAddr0;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR1 */
+	uint32_t EmcDllXformAddr1;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR2 */
+	uint32_t EmcDllXformAddr2;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR3 */
+	uint32_t EmcDllXformAddr3;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR4 */
+	uint32_t EmcDllXformAddr4;
+	/* Specifies the value for EMC_DLL_XFORM_ADDR5 */
+	uint32_t EmcDllXformAddr5;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE8 */
+	uint32_t EmcDllXformQUse8;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE9 */
+	uint32_t EmcDllXformQUse9;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE10 */
+	uint32_t EmcDllXformQUse10;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE11 */
+	uint32_t EmcDllXformQUse11;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE12 */
+	uint32_t EmcDllXformQUse12;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE13 */
+	uint32_t EmcDllXformQUse13;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE14 */
+	uint32_t EmcDllXformQUse14;
+	/* Specifies the value for EMC_DLL_XFORM_QUSE15 */
+	uint32_t EmcDllXformQUse15;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS0 */
+	uint32_t EmcDliTrimTxDqs0;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS1 */
+	uint32_t EmcDliTrimTxDqs1;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS2 */
+	uint32_t EmcDliTrimTxDqs2;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS3 */
+	uint32_t EmcDliTrimTxDqs3;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS4 */
+	uint32_t EmcDliTrimTxDqs4;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS5 */
+	uint32_t EmcDliTrimTxDqs5;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS6 */
+	uint32_t EmcDliTrimTxDqs6;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS7 */
+	uint32_t EmcDliTrimTxDqs7;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS8 */
+	uint32_t EmcDliTrimTxDqs8;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS9 */
+	uint32_t EmcDliTrimTxDqs9;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS10 */
+	uint32_t EmcDliTrimTxDqs10;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS11 */
+	uint32_t EmcDliTrimTxDqs11;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS12 */
+	uint32_t EmcDliTrimTxDqs12;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS13 */
+	uint32_t EmcDliTrimTxDqs13;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS14 */
+	uint32_t EmcDliTrimTxDqs14;
+	/* Specifies the value for EMC_DLI_TRIM_TXDQS15 */
+	uint32_t EmcDliTrimTxDqs15;
+	/* Specifies the value for EMC_DLL_XFORM_DQ0 */
+	uint32_t EmcDllXformDq0;
+	/* Specifies the value for EMC_DLL_XFORM_DQ1 */
+	uint32_t EmcDllXformDq1;
+	/* Specifies the value for EMC_DLL_XFORM_DQ2 */
+	uint32_t EmcDllXformDq2;
+	/* Specifies the value for EMC_DLL_XFORM_DQ3 */
+	uint32_t EmcDllXformDq3;
+	/* Specifies the value for EMC_DLL_XFORM_DQ4 */
+	uint32_t EmcDllXformDq4;
+	/* Specifies the value for EMC_DLL_XFORM_DQ5 */
+	uint32_t EmcDllXformDq5;
+	/* Specifies the value for EMC_DLL_XFORM_DQ6 */
+	uint32_t EmcDllXformDq6;
+	/* Specifies the value for EMC_DLL_XFORM_DQ7 */
+	uint32_t EmcDllXformDq7;
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	uint32_t WarmBootWait;
+
+	/* Specifies the value for EMC_CTT_TERM_CTRL */
+	uint32_t EmcCttTermCtrl;
+
+	/* Specifies the value for EMC_ODT_WRITE */
+	uint32_t EmcOdtWrite;
+	/* Specifies the value for EMC_ODT_WRITE */
+	uint32_t EmcOdtRead;
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	uint32_t EmcZcalInterval;
+	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
+	uint32_t EmcZcalWaitCnt;
+	/* Specifies the value for EMC_ZCAL_MRW_CMD */
+	uint32_t EmcZcalMrwCmd;
+
+	/* DRAM initialization sequence flow control */
+
+	/* Specifies the MRS command value for resetting DLL */
+	uint32_t EmcMrsResetDll;
+	/* Specifies the command for ZQ initialization of device 0 */
+	uint32_t EmcZcalInitDev0;
+	/* Specifies the command for ZQ initialization of device 1 */
+	uint32_t EmcZcalInitDev1;
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	uint32_t EmcZcalInitWait;
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	uint32_t EmcZcalWarmColdBootEnables;
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	uint32_t EmcMrwLpddr2ZcalWarmBoot;
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	uint32_t EmcZqCalDdr3WarmBoot;
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	uint32_t EmcZcalWarmBootWait;
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	uint32_t EmcMrsWarmBootEnable;
+	/*
+	 * Specifies the wait time after sending an MRS DLL reset command
+	 * in microseconds)
+	 */
+	uint32_t EmcMrsResetDllWait;
+	/* Specifies the extra MRS command to initialize mode registers */
+	uint32_t EmcMrsExtra;
+	/* Specifies the extra MRS command at warm boot */
+	uint32_t EmcWarmBootMrsExtra;
+	/* Specifies the EMRS command to enable the DDR2 DLL */
+	uint32_t EmcEmrsDdr2DllEnable;
+	/* Specifies the MRS command to reset the DDR2 DLL */
+	uint32_t EmcMrsDdr2DllReset;
+	/* Specifies the EMRS command to set OCD calibration */
+	uint32_t EmcEmrsDdr2OcdCalib;
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	uint32_t EmcDdr2Wait;
+	/* Specifies the value for EMC_CLKEN_OVERRIDE */
+	uint32_t EmcClkenOverride;
+	/* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */
+	uint32_t McDisExtraSnapLevels;
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	uint32_t EmcExtraRefreshNum;
+	/* Specifies the master override for all EMC clocks */
+	uint32_t EmcClkenOverrideAllWarmBoot;
+	/* Specifies the master override for all MC clocks */
+	uint32_t McClkenOverrideAllWarmBoot;
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	uint32_t EmcCfgDigDllPeriodWarmBoot;
+
+	/* Pad controls */
+
+	/* Specifies the value for PMC_VDDP_SEL */
+	uint32_t PmcVddpSel;
+	/* Specifies the wait time after programming PMC_VDDP_SEL */
+	uint32_t PmcVddpSelWait;
+	/* Specifies the value for PMC_DDR_PWR */
+	uint32_t PmcDdrPwr;
+	/* Specifies the value for PMC_DDR_CFG */
+	uint32_t PmcDdrCfg;
+	/* Specifies the value for PMC_IO_DPD3_REQ */
+	uint32_t PmcIoDpd3Req;
+	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
+	uint32_t PmcIoDpd3ReqWait;
+	/* Specifies the value for PMC_REG_SHORT */
+	uint32_t PmcRegShort;
+	/* Specifies the value for PMC_NO_IOPOWER */
+	uint32_t PmcNoIoPower;
+	/* Specifies the wait time after programming PMC_POR_DPD_CTRL */
+	uint32_t PmcPorDpdCtrlWait;
+	/* Specifies the value for EMC_XM2CMDPADCTRL */
+	uint32_t EmcXm2CmdPadCtrl;
+	/* Specifies the value for EMC_XM2CMDPADCTRL2 */
+	uint32_t EmcXm2CmdPadCtrl2;
+	/* Specifies the value for EMC_XM2CMDPADCTRL3 */
+	uint32_t EmcXm2CmdPadCtrl3;
+	/* Specifies the value for EMC_XM2CMDPADCTRL4 */
+	uint32_t EmcXm2CmdPadCtrl4;
+	/* Specifies the value for EMC_XM2CMDPADCTRL5 */
+	uint32_t EmcXm2CmdPadCtrl5;
+	/* Specifies the value for EMC_XM2DQSPADCTRL */
+	uint32_t EmcXm2DqsPadCtrl;
+	/* Specifies the value for EMC_XM2DQSPADCTRL2 */
+	uint32_t EmcXm2DqsPadCtrl2;
+	/* Specifies the value for EMC_XM2DQSPADCTRL3 */
+	uint32_t EmcXm2DqsPadCtrl3;
+	/* Specifies the value for EMC_XM2DQSPADCTRL4 */
+	uint32_t EmcXm2DqsPadCtrl4;
+	/* Specifies the value for EMC_XM2DQSPADCTRL5 */
+	uint32_t EmcXm2DqsPadCtrl5;
+	/* Specifies the value for EMC_XM2DQSPADCTRL6 */
+	uint32_t EmcXm2DqsPadCtrl6;
+	/* Specifies the value for EMC_XM2DQPADCTRL */
+	uint32_t EmcXm2DqPadCtrl;
+	/* Specifies the value for EMC_XM2DQPADCTRL2 */
+	uint32_t EmcXm2DqPadCtrl2;
+	/* Specifies the value for EMC_XM2DQPADCTRL3 */
+	uint32_t EmcXm2DqPadCtrl3;
+	/* Specifies the value for EMC_XM2CLKPADCTRL */
+	uint32_t EmcXm2ClkPadCtrl;
+	/* Specifies the value for EMC_XM2CLKPADCTRL2 */
+	uint32_t EmcXm2ClkPadCtrl2;
+	/* Specifies the value for EMC_XM2COMPPADCTRL */
+	uint32_t EmcXm2CompPadCtrl;
+	/* Specifies the value for EMC_XM2VTTGENPADCTRL */
+	uint32_t EmcXm2VttGenPadCtrl;
+	/* Specifies the value for EMC_XM2VTTGENPADCTRL2 */
+	uint32_t EmcXm2VttGenPadCtrl2;
+	/* Specifies the value for EMC_XM2VTTGENPADCTRL3 */
+	uint32_t EmcXm2VttGenPadCtrl3;
+	/* Specifies the value for EMC_ACPD_CONTROL */
+	uint32_t EmcAcpdControl;
+
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
+	uint32_t EmcSwizzleRank0ByteCfg;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
+	uint32_t EmcSwizzleRank0Byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
+	uint32_t EmcSwizzleRank0Byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
+	uint32_t EmcSwizzleRank0Byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
+	uint32_t EmcSwizzleRank0Byte3;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
+	uint32_t EmcSwizzleRank1ByteCfg;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
+	uint32_t EmcSwizzleRank1Byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
+	uint32_t EmcSwizzleRank1Byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
+	uint32_t EmcSwizzleRank1Byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
+	uint32_t EmcSwizzleRank1Byte3;
+
+	/* Specifies the value for EMC_DSR_VTTGEN_DRV */
+	uint32_t EmcDsrVttgenDrv;
+
+	/* Specifies the value for EMC_TXDSRVTTGEN */
+	uint32_t EmcTxdsrvttgen;
+	/* Specifies the value for EMC_BGBIAS_CTL */
+	uint32_t EmcBgbiasCtl0;
+
+	/* DRAM size information */
+
+	/* Specifies the value for MC_EMEM_ADR_CFG */
+	uint32_t McEmemAdrCfg;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
+	uint32_t McEmemAdrCfgDev0;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
+	uint32_t McEmemAdrCfgDev1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
+	uint32_t McEmemAdrCfgBankMask0;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
+	uint32_t McEmemAdrCfgBankMask1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
+	uint32_t McEmemAdrCfgBankMask2;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */
+	uint32_t McEmemAdrCfgBankSwizzle3;
+
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in KBytes)
+	 */
+	uint32_t McEmemCfg;
+
+	/* MC arbitration configuration */
+
+	/* Specifies the value for MC_EMEM_ARB_CFG */
+	uint32_t McEmemArbCfg;
+	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
+	uint32_t McEmemArbOutstandingReq;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
+	uint32_t McEmemArbTimingRcd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
+	uint32_t McEmemArbTimingRp;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
+	uint32_t McEmemArbTimingRc;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
+	uint32_t McEmemArbTimingRas;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
+	uint32_t McEmemArbTimingFaw;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
+	uint32_t McEmemArbTimingRrd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
+	uint32_t McEmemArbTimingRap2Pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
+	uint32_t McEmemArbTimingWap2Pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
+	uint32_t McEmemArbTimingR2R;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
+	uint32_t McEmemArbTimingW2W;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
+	uint32_t McEmemArbTimingR2W;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
+	uint32_t McEmemArbTimingW2R;
+	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
+	uint32_t McEmemArbDaTurns;
+	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
+	uint32_t McEmemArbDaCovers;
+	/* Specifies the value for MC_EMEM_ARB_MISC0 */
+	uint32_t McEmemArbMisc0;
+	/* Specifies the value for MC_EMEM_ARB_MISC1 */
+	uint32_t McEmemArbMisc1;
+	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
+	uint32_t McEmemArbRing1Throttle;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
+	uint32_t McEmemArbOverride;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
+	uint32_t McEmemArbOverride1;
+	/* Specifies the value for MC_EMEM_ARB_RSV */
+	uint32_t McEmemArbRsv;
+
+	/* Specifies the value for MC_CLKEN_OVERRIDE */
+	uint32_t McClkenOverride;
+
+	/* Specifies the value for MC_STAT_CONTROL */
+	uint32_t McStatControl;
+	/* Specifies the value for MC_DISPLAY_SNAP_RING */
+	uint32_t McDisplaySnapRing;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
+	uint32_t McVideoProtectBom;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
+	uint32_t McVideoProtectBomAdrHi;
+	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
+	uint32_t McVideoProtectSizeMb;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
+	uint32_t McVideoProtectVprOverride;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
+	uint32_t McVideoProtectVprOverride1;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
+	uint32_t McVideoProtectGpuOverride0;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
+	uint32_t McVideoProtectGpuOverride1;
+	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
+	uint32_t McSecCarveoutBom;
+	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
+	uint32_t McSecCarveoutAdrHi;
+	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
+	uint32_t McSecCarveoutSizeMb;
+	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
+	   VIDEO_PROTECT_WRITE_ACCESS */
+	uint32_t McVideoProtectWriteAccess;
+	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
+	   SEC_CARVEOUT_WRITE_ACCESS */
+	uint32_t McSecCarveoutProtectWriteAccess;
+
+	/* Specifies enable for CA training */
+	uint32_t EmcCaTrainingEnable;
+	/* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */
+	uint32_t EmcCaTrainingTimingCntl1;
+	/* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */
+	uint32_t EmcCaTrainingTimingCntl2;
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.
+	   spec packet SWIZZLE_BIT6_GT_BIT7 */
+	uint32_t SwizzleRankByteEncode;
+	/* Specifies enable and offset for patched boot rom write */
+	uint32_t BootRomPatchControl;
+	/* Specifies data for patched boot rom write */
+	uint32_t BootRomPatchData;
+	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
+	uint32_t McMtsCarveoutBom;
+	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
+	uint32_t McMtsCarveoutAdrHi;
+	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
+	uint32_t McMtsCarveoutSizeMb;
+	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
+	uint32_t McMtsCarveoutRegCtrl;
+
+	/* End of generated code by warmboot_code_gen */
+};
+
+check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0);
+
+#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ */