soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart

The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So  configure_stoneyridge_uart()
became redundant. Remove procedure  configure_stoneyridge_uart().

BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.

Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 17 insertions, 15 deletions

diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c
index 2d73ee08d2..c274a76bc6 100644
--- a/src/mainboard/amd/gardenia/gpio.c
+++ b/src/mainboard/amd/gardenia/gpio.c
@@ -35,6 +35,16 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
 	{GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT },
 	/* SD power */
 	{GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
+	/* GPIO_136 - UART0_FCH_RX_DEBUG_RX */
+	{GPIO_136, Function0, INPUT },
+	/* GPIO_137 - UART0_FCH_DEBUG_RTS */
+	{GPIO_137, Function0, INPUT },
+	/* GPIO_138 - UART0_FCH_TX_DEBUG_RX */
+	{GPIO_138, Function0, INPUT },
+	/* GPIO_142 - UART1_FCH_RTS */
+	{GPIO_142, Function0, INPUT },
+	/* GPIO_143 - UART1_FCH_TX */
+	{GPIO_143, Function0, INPUT },
 };
 
 const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
index d1cc017c93..2f40546427 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -53,6 +53,12 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
 	/* BD_ID1 */
 	{GPIO_135, Function1, INPUT },
 
+	/* GPIO_136 - UART_FCH_RX_DEBUG_RX */
+	{GPIO_136, Function0, INPUT },
+
+	/* GPIO_138 - UART_FCH_TX_DEBUG_RX */
+	{GPIO_138, Function0, INPUT },
+
 	/* TPM_SERIRQ# */
 	{GPIO_139, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT },
 
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 3eff5eb0dc..fafaf079ce 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -75,8 +75,6 @@ void bootblock_soc_early_init(void)
 	bootblock_fch_early_init();
 
 	post_code(0x90);
-	if (CONFIG_STONEYRIDGE_UART)
-		configure_stoneyridge_uart();
 }
 
 /*
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 6dea0c6864..bdcb38fa8d 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -353,7 +353,6 @@ struct stoneyridge_aoac {
 
 void enable_aoac_devices(void);
 void sb_enable_rom(void);
-void configure_stoneyridge_uart(void);
 void configure_stoneyridge_i2c(void);
 void sb_clk_output_48Mhz(void);
 void sb_disable_4dw_burst(void);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index cf059a46b2..55e39569d0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -36,9 +36,7 @@
  * Table of devices that need their AOAC registers enabled and waited
  * upon (usually about .55 milliseconds). Instead of individual delays
  * waiting for each device to become available, a single delay will be
- * executed at configure_stoneyridge_uart(). All other devices need only
- * to verify if their AOAC is already enabled, and do a minimal delay
- * if needed.
+ * executed.
  */
 const static struct stoneyridge_aoac aoac_devs[] = {
 	{ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
@@ -331,15 +329,6 @@ void enable_aoac_devices(void)
 	} while (!status);
 }
 
-void configure_stoneyridge_uart(void)
-{
-	/* Set the GPIO mux to UART */
-	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
-	write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
-	write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
-	write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
-}
-
 void sb_pci_port80(void)
 {
 	u8 byte;