diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-29 22:08:01 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-29 22:08:01 +0000 |
| commit | 798ef2893c44ce3194c539c8c5db33d11e8edbac (patch) | |
| tree | 405318f804b41070e16ca6b907d65a1e27cc5071 /src | |
| parent | 72bdfeb6987f9578ac7fee3f21140ab5853d6179 (diff) | |
| download | coreboot-798ef2893c44ce3194c539c8c5db33d11e8edbac.tar.xz | |
This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run
awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c
cut some holes into the source.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
123 files changed, 105 insertions, 482 deletions
diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 393cdcf0ad..4173df22fa 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index fbceb6fdd5..25e0b3bbfc 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index f3082892f1..95ba4b69fd 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index 3bcb063a2d..1ee8aadf74 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> @@ -46,3 +43,4 @@ static void main(unsigned long bist) sdram_init(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 640dc4984f..1547dc4da3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -87,7 +84,6 @@ static const struct msrinit msr_table[] = {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF }; - static void msr_init(void) { int i; @@ -133,3 +129,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 872cb2f0a3..8decf4c7c2 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -179,7 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); @@ -198,3 +194,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 0c25cf6b77..f9ca92fac1 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -196,3 +193,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index f9259cd43a..332e256085 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -17,15 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - - //#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 1 @@ -71,7 +66,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #define printk(BIOS_INFO, fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) #include "cpu/x86/bist.h" - static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" @@ -86,17 +80,14 @@ static void memreset_setup(void) { } - static void memreset(int controllers, const struct mem_controller *ctrl) { } - static void activate_spd_rom(const struct mem_controller *ctrl) { } - static int spd_read_byte(u32 device, u32 address) { int result; @@ -118,7 +109,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" - #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" @@ -281,7 +271,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); @@ -292,3 +281,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 19c5b17ade..6337e89c2c 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -132,3 +130,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index e38c63916c..d4dcca3822 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -208,3 +205,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index ea3ec908fa..087fe1842a 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -118,7 +115,6 @@ static void msr_init(void) /* put code in northbridge[init].c here */ } - static void main(unsigned long bist) { static const struct mem_controller memctrl [] = { @@ -146,3 +142,4 @@ static void main(unsigned long bist) /* Check all of memory */ //ram_check(0x00000000, 640*1024); } + diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index d4d3c46c0c..247e920b95 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -32,7 +29,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" - #if 0 static void post_code(uint8_t value) { #if 1 @@ -50,8 +46,6 @@ static void post_code(uint8_t value) { #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" - - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -142,7 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -330,3 +323,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } + diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index e628304445..4d86535bbe 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -17,15 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - - #define SYSTEM_TYPE 0 /* SERVER */ //#define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 1 @@ -71,7 +66,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #endif #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -87,12 +81,10 @@ static void memreset_setup(void) outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } - static void memreset(int controllers, const struct mem_controller *ctrl) { } - static void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 @@ -109,7 +101,6 @@ static void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } - static int spd_read_byte(u32 device, u32 address) { int result; @@ -131,7 +122,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -244,7 +234,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); @@ -254,7 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); - /* FIXME: Move this to chipset init. enable cf9 for hard reset */ print_debug("enable_cf9_x()\n"); @@ -266,12 +254,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); - printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); post_code(0x3E); - memreset_setup(); post_code(0x40); @@ -281,7 +267,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); @@ -292,7 +277,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); post_code(0x42); @@ -300,6 +284,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. - } diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index ae9e3db666..975d259d49 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -169,3 +166,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index fea9925d37..d55330274d 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -38,7 +35,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" - #define POST_CODE(x) outb(x, 0x80) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -47,7 +43,6 @@ #define DIMM0 0xA0 #define DIMM1 0xA2 - static int spd_read_byte(unsigned device, unsigned address) { int i; @@ -182,3 +177,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot */ return; } + diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index b7641d8fe0..427911260a 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> @@ -46,3 +43,4 @@ static void main(unsigned long bist) sdram_init(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index a494b582db..d4d3be9d1d 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -55,3 +52,4 @@ static void main(unsigned long bist) /* Check whether RAM works. */ /* ram_check(0x00000000, 0x4000); */ } + diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 54aedc7ba3..61e6b5450c 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -21,9 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - /* Used by it8712f_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) @@ -195,3 +192,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 91a430b4e9..7e9b6fc4dd 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -22,9 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -259,3 +256,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } + diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 9bb4c8d1b3..81971914ce 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -22,9 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -92,7 +89,6 @@ void activate_spd_rom(const struct mem_controller *ctrl) #define K8_4RANK_DIMM_SUPPORT 1 - #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/raminit_f.c" @@ -117,7 +113,6 @@ static void ldtstop_sb(void) print_debug("done\r\n"); } - #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" @@ -195,7 +190,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_info("now booting... real_main\r\n"); - if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -234,7 +228,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ /* allow LDT STOP asserts */ vt8237_sb_enable_fid_vid(); @@ -254,3 +247,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } + diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index e21a7c6db5..2345346353 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -66,3 +63,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 9d429db864..82076e546f 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -68,3 +65,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index a4a37c942a..3ccd8ec096 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index b8df5f66db..676c8e27e1 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 21a49e1703..eeb46e0a01 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index a40d39a738..44cfb2ca82 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -73,3 +70,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 52cdf81f1e..dbee44d893 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e161ef109f..671bde17d4 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index 94564d004c..0e828fe996 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -47,3 +44,4 @@ static void main(unsigned long bist) sdram_init(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index 9f7bbe51bf..dc960d8cee 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index 669329d97d..07f5ad5a92 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -55,3 +52,4 @@ static void main(unsigned long bist) /* Check whether RAM works. */ /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 3b76de1617..90de05a1f6 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -126,3 +123,4 @@ static void main(unsigned long bist) print_spew("Leaving romstage.c:main()\r\n"); } + diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index b3b07ae596..525e2c561c 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 11d5bb4cf5..d67b713451 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 @@ -215,3 +212,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 9c08d1b628..1d9826dd7b 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -74,3 +71,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 4c04ecfaee..37b28aace6 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -25,7 +23,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" - #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -59,7 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" - /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere */ @@ -71,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define ipmidata 0xca0 #define ipmicsr 0xca4 - static inline void ibfzero(void) { while(inb(ipmicsr) & (1<<IBF)) @@ -290,7 +285,6 @@ static void main(unsigned long bist) uart_init(); console_init(); - /* stuff we seem to need */ pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); @@ -371,3 +365,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index b7d8fd0f10..1e0a8dcc47 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> @@ -46,8 +44,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } - - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -83,7 +79,6 @@ static void main(unsigned long bist) uart_init(); console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -99,7 +94,6 @@ static void main(unsigned long bist) // dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); @@ -142,3 +136,4 @@ static void main(unsigned long bist) #endif */ } + diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 918aef59c2..8db527d52b 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> @@ -45,8 +43,6 @@ void setup_pars(void) typedef void (*lj)(void); - - struct mem_controller { int i; }; @@ -59,8 +55,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } - - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -90,7 +84,6 @@ static inline void dumpmem(void){ } } - static inline void irqinit(void){ volatile unsigned char *cp; #if 0 @@ -186,15 +179,12 @@ static inline void irqinit(void){ #endif } - - static void main(unsigned long bist) { volatile int i; for(i = 0; i < 100; i++) ; - setupsc520(); irqinit(); uart_init(); @@ -213,7 +203,6 @@ static void main(unsigned long bist) outb(0xee, 0x80); print_err("loop forever ...\n"); - #if 0 /* clear memory 1meg */ diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index c7dde03ef0..9d5d431f39 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -118,3 +115,4 @@ void cache_as_ram_main(void) void done_cache_as_ram_main(void); done_cache_as_ram_main(); } + diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index fe41cce3e7..6fa43e3fe3 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -57,3 +54,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index 9739d06eab..02d7350626 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -26,3 +24,4 @@ static void main(void) //print_pci_devices(); //dump_pci_devices(); } + diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index af3f873bc1..d5c671fdd5 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 915122f879..f55ee1b789 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -21,9 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 @@ -147,7 +144,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { @@ -212,7 +208,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if CONFIG_USBDEBUG_DIRECT sis966_enable_usbdebug_direct(DBGP_DEFAULT); early_usbdebug_direct_init(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index fe5b30169b..a03e839d6f 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 @@ -146,7 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { @@ -167,7 +163,6 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -226,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if CONFIG_USBDEBUG_DIRECT mcp55_enable_usbdebug_direct(DBGP_DEFAULT); early_usbdebug_direct_init(); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index c9020c5944..6b617afdfa 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -25,9 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 @@ -60,7 +57,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" - #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -79,7 +75,6 @@ #include "superio/serverengines/pilot/pilot_early_init.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -139,7 +134,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -218,7 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pc87417_enable_dev(RTC_DEV); } - if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } @@ -232,7 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - console_init(); // setup_early_ipmi_serial(); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 09e3680ee7..ac8d8b8a84 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -66,3 +63,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 8af9cffd0c..a9dccf0dcf 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -59,7 +57,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -92,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -167,3 +163,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 751b20b56f..1843a8fbba 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -59,7 +57,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -166,3 +163,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index bb649322c3..f4a40e8b76 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -61,3 +58,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0x00000000, 640 * 1024); */ } + diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 69e2a28c38..e25b889e3b 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -56,3 +53,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0x00000000, 640 * 1024); */ } + diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 7af5d8c158..3f2435d69b 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -135,3 +132,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index ab3576c944..48f3f78e7b 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -19,7 +19,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. - /* Configuration of the i945 driver */ #define CHIPSET_I945GC 1 #define CHANNEL_XOR_RANDOMIZATION 1 @@ -98,7 +97,6 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); } - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 6d3673689a..7eb83c9153 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -20,8 +20,6 @@ * MA 02110-1301 USA */ - - #include <delay.h> #include <stdint.h> @@ -236,3 +234,4 @@ void real_main(unsigned long bist) /* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */ #include "cpu/intel/model_6ex/cache_as_ram_disable.c" + diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 4660b136dc..04b552fb25 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -53,7 +51,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "debug.c" - static void main(unsigned long bist) { /* @@ -150,3 +147,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 7ff8ed9494..f23169736b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -18,8 +18,6 @@ * */ -#define ASSEMBLY 1 - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -61,7 +59,6 @@ static inline int spd_read_byte(u16 device, u8 address) #include "lib/generic_sdram.c" #include "../jarrell/debug.c" - static void main(unsigned long bist) { msr_t msr; @@ -126,3 +123,4 @@ static void main(unsigned long bist) ram_check(0, 1024 * 1024); } + diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 0559ecb4f4..b2e04be896 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -18,8 +18,6 @@ * */ -#define ASSEMBLY 1 - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -113,3 +111,4 @@ static void main(unsigned long bist) ram_verify(0x00000000, 0x02000000); #endif } + diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 157a9f4719..240e917964 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -44,7 +41,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" - // This function MUST appear last (ROMCC limitation) static void main(unsigned long bist) { @@ -92,3 +88,4 @@ static void main(unsigned long bist) // if the following line is removed. print_debug("SDRAM is up.\r\n"); } + diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 1eb98fc4ce..1f865adf0c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -39,7 +36,6 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -117,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -193,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - #if K8_SET_FIDVID == 1 { @@ -245,7 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - #if 0 dump_pci_devices(); #endif @@ -253,3 +246,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } + diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index f04e3eac86..55ba27a09c 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -39,7 +36,6 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -117,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -193,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - #if K8_SET_FIDVID == 1 { @@ -245,7 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - #if 0 dump_pci_devices(); #endif @@ -253,3 +246,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } + diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index c46bdebef4..55ba27a09c 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -116,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -192,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - #if K8_SET_FIDVID == 1 { @@ -244,7 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - #if 0 dump_pci_devices(); #endif @@ -252,3 +246,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } + diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index b37b305d48..ac3ab97f91 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -128,3 +125,4 @@ static void main(unsigned long bist) print_spew("Leaving romstage.c:main()\r\n"); } + diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c7f1ee9b04..121eb143f0 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -19,7 +19,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. - /* Configuration of the i945 driver */ #define CHIPSET_I945GM 1 /* Usually system firmware turns off system memory clock signals to @@ -112,7 +111,6 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 6d80c237c3..28df9b74bc 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -182,7 +179,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); @@ -201,3 +197,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 1ea608f735..c5ed73aec6 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -70,12 +67,10 @@ static void msr_init(void) __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f); __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000); - __builtin_wrmsr(0x50002001, 0x27, 0x0); __builtin_wrmsr(0x4c002001, 0x1, 0x0); } - static void main(unsigned long bist) { static const struct mem_controller memctrl [] = { @@ -104,7 +99,6 @@ static void main(unsigned long bist) outb( 0x87, 0x4E); //enter SuperIO configuration mode outb( 0x87, 0x4E); - outb(0x20, 0x4e); temp = inb(0x4f); print_debug_hex8(temp); @@ -134,3 +128,4 @@ static void main(unsigned long bist) // ram_check(0x00000000, 640*1024); } + diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index c288fc3342..3884d28c86 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -21,9 +21,6 @@ /* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */ -#define ASSEMBLY 1 - - #include <stdlib.h> #include <stdint.h> #include <device/pci_def.h> @@ -167,3 +164,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 692c5a75e0..e92cf7adc7 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -21,9 +21,6 @@ /* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */ -#define ASSEMBLY 1 - - #include <stdlib.h> #include <stdint.h> #include <spd.h> @@ -236,3 +233,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index fc60ad21cc..d06bfdd11a 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -67,3 +64,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 0d65058d1f..f061cb5460 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 570a360d93..b250994939 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -78,3 +75,4 @@ static void main(unsigned long bist) ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */ #endif } + diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index e3e3e2ef55..e5a6bf9fe4 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 0441630ca7..4a558eba6c 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -67,3 +64,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index e4372e41db..80f217c363 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -22,9 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1) /* Used by raminit. */ @@ -199,3 +196,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 725f0f6bd3..9016075fb9 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -20,9 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - // #define CACHE_AS_RAM_ADDRESS_DEBUG 1 // #define RAM_TIMING_DEBUG 1 // #define DQS_TRAIN_DEBUG 1 diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index d0b7ebde77..cf625e5561 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -23,9 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -72,7 +69,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" @@ -112,8 +108,6 @@ static inline void change_i2c_mux(unsigned device) } #endif - - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -145,7 +139,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -231,7 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bcm5785_early_setup(); - #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); @@ -315,5 +307,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); - } + diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 41f18e2fc8..270924392a 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -22,9 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -136,7 +133,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { @@ -152,7 +148,6 @@ static void sio_setup(void) dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - } //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. @@ -243,3 +238,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 270034c324..9ebf659492 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define FAM10_SCAN_PCI_BUS 0 diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index f612e03ba5..9f03a6e594 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -60,3 +57,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 65af0ae1e5..7ee9d1600a 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -3,7 +3,6 @@ * Adapted by Stefan Reinauer <stepan@coresystems.de> * Additional (C) 2007 coresystems GmbH */ -#define ASSEMBLY 1 #include <stdint.h> @@ -100,14 +99,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "cpu/amd/dualcore/dualcore.c" - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -175,7 +172,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); @@ -194,3 +190,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 40a2df7448..daaf84550d 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 @@ -146,7 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { @@ -212,7 +208,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if CONFIG_USBDEBUG_DIRECT mcp55_enable_usbdebug_direct(DBGP_DEFAULT); early_usbdebug_direct_init(); diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c index 12ff739a4e..c47ed79594 100644 --- a/src/mainboard/olpc/btest/romstage.c +++ b/src/mainboard/olpc/btest/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -38,9 +35,6 @@ static inline unsigned int fls(unsigned int x) return r; } - - - /* sdram parameters for OLPC: row address = 13 col address = 9 @@ -192,3 +186,4 @@ static void main(unsigned long bist) /* Check all of memory */ //ram_check(0x00000000, 640*1024); } + diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c index 12ff739a4e..c47ed79594 100644 --- a/src/mainboard/olpc/rev_a/romstage.c +++ b/src/mainboard/olpc/rev_a/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -38,9 +35,6 @@ static inline unsigned int fls(unsigned int x) return r; } - - - /* sdram parameters for OLPC: row address = 13 col address = 9 @@ -192,3 +186,4 @@ static void main(unsigned long bist) /* Check all of memory */ //ram_check(0x00000000, 640*1024); } + diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 5d83cad394..764400c98a 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <spd.h> #include <device/pci_def.h> @@ -210,3 +207,4 @@ void cache_as_ram_main(void) void done_cache_as_ram_main(void); done_cache_as_ram_main(); } + diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 9e4915f753..a7635ee8ac 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -133,3 +130,4 @@ static void main(unsigned long bist) /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ } + diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 151e6ccea2..3a2c672b51 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -21,7 +21,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. - /* Configuration of the i945 driver */ #define CHIPSET_I945GM 1 #define CHANNEL_XOR_RANDOMIZATION 1 @@ -79,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } - #include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.c" #include "northbridge/intel/i945/errata.c" @@ -102,7 +100,6 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); } - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 424d316083..cbf4bd3ea0 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 56ccd76336..e006a74680 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -1,7 +1,3 @@ -#define ASSEMBLY 1 - - - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 @@ -78,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } - #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" @@ -111,11 +106,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { @@ -217,3 +210,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index f341678339..a9c3ef4afa 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -16,9 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 0aed8b9c75..552098d230 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 @@ -77,7 +74,6 @@ #include "cpu/amd/mtrr/amd_earlymtrr.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -135,7 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 1221f38f5c..068e27f16d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define FAM10_SCAN_PCI_BUS 0 @@ -70,7 +67,6 @@ #include "cpu/amd/mtrr/amd_earlymtrr.c" - #include "northbridge/amd/amdfam10/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -126,7 +122,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" - static void sio_setup(void) { @@ -194,7 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "\n"); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -293,7 +287,6 @@ post_code(0x3E); post_code(0x40); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index a9af4b57f4..a65fd34456 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define FAM10_SCAN_PCI_BUS 0 @@ -71,7 +68,6 @@ #include "cpu/amd/mtrr/amd_earlymtrr.c" - #include "northbridge/amd/amdfam10/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -130,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" - static void sio_setup(void) { @@ -337,7 +332,6 @@ post_code(0x3E); post_code(0x40); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 8fc496773e..0b274c1947 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -24,7 +22,6 @@ #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" - #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -55,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7525/raminit.c" #include "lib/generic_sdram.c" - static void main(unsigned long bist) { /* @@ -139,3 +135,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 9d5d8af506..5cbb83074e 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -25,7 +23,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" - #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -56,7 +53,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" - static void main(unsigned long bist) { /* @@ -150,3 +146,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 0f1041013d..4af2a54131 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -25,7 +23,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" - #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -56,7 +53,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" - static void main(unsigned long bist) { /* @@ -151,3 +147,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 4c4f2f19ac..7ddb2c46d7 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -25,7 +23,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" - #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -57,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" - static void main(unsigned long bist) { /* @@ -152,3 +148,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 8e46e928fe..38c06d5000 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -25,7 +23,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" - #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -57,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" - static void main(unsigned long bist) { /* @@ -152,3 +148,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index a222a1a243..309016e787 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -186,7 +183,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); @@ -214,3 +210,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 1abb97c775..769f674a91 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -111,7 +108,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -181,7 +177,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); @@ -200,3 +195,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index a5c76fd037..b5db71d3eb 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -4,8 +4,6 @@ * (c) 2006 coresystems GmbH */ -#define ASSEMBLY 1 - #define ASM_CONSOLE_LOGLEVEL 6 #include <stdint.h> #include <device/pci_def.h> diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index 669329d97d..07f5ad5a92 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -55,3 +52,4 @@ static void main(unsigned long bist) /* Check whether RAM works. */ /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index f8ad96350b..50a6335fb4 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <stdlib.h> #include <device/pci_def.h> @@ -135,3 +132,4 @@ static void main(unsigned long bist) /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ } + diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index af9e582639..6c1ba5891a 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -71,3 +68,4 @@ static void main(unsigned long bist) sdram_enable(); /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index c339740bde..8ca9c5cba5 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -72,12 +70,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } - #include "northbridge/intel/e7501/raminit.c" #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" - #include "cpu/x86/car/copy_and_run.c" void amd64_main(unsigned long bist) @@ -135,7 +131,6 @@ void amd64_main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0, 0)); #endif - #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -222,7 +217,7 @@ cpu_reset_x: } #endif - print_debug("should not be here -\r\n"); } + diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index cf0b71edcc..22eecc9ec9 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -157,3 +155,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 26c291cfd5..e57c3642b5 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -157,3 +155,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index b5565fb35a..2dbcdbebf1 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -15,7 +13,6 @@ #include "arch/i386/lib/console.c" #include "lib/ramtest.c" - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" @@ -159,3 +156,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index bbe6d68e0a..b47bf584e8 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 @@ -83,7 +80,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } - #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -91,7 +87,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -186,3 +181,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 3d27fce4cf..d801abbdc9 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -163,3 +161,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 3dd5fb7194..a6e4f8e2cc 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -91,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "cpu/amd/dualcore/dualcore.c" - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -165,7 +162,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); @@ -184,3 +180,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index bc0ccb9db7..838c71c316 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -203,3 +200,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 7ccffc076a..099c29aa36 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 @@ -172,3 +169,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 2d38b635d4..98ac94c3e1 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 @@ -217,3 +214,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 1e2f725198..0db72dff24 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 @@ -144,7 +141,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - static void sio_setup(void) { @@ -208,7 +204,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if CONFIG_USBDEBUG_DIRECT mcp55_enable_usbdebug_direct(DBGP_DEFAULT); early_usbdebug_direct_init(); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index caf6c18dac..9081945511 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define FAM10_SCAN_PCI_BUS 0 diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 49f7f16a19..804531b0cd 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -208,3 +206,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index a3ee6cd641..6dd2b042b0 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -1,5 +1,3 @@ -#define ASSEMBLY 1 - #include <stdint.h> #include <string.h> @@ -33,7 +31,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - #include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) @@ -199,3 +196,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 57bc0dec18..1c4969c322 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -123,3 +120,4 @@ static void main(unsigned long bist) print_spew("Leaving romstage.c:main()\r\n"); } + diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 10d665fda6..9dcb4a8939 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -152,3 +149,4 @@ static void main(unsigned long bist) print_spew("Leaving romstage.c:main()\r\n"); } + diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index f182c73cc5..451a7ba7e1 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -22,8 +22,6 @@ * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch. */ -#define ASSEMBLY 1 - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -814,3 +812,4 @@ cpu_reset_x: print_debug("should not be here -\r\n"); } + diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index c98a663c61..5f3ebc3210 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -57,7 +54,6 @@ static const struct mem_controller ctrl = { .channel0 = { 0x50 }, }; - static void memreset_setup(void) { } @@ -146,7 +142,6 @@ static void main(unsigned long bist) print_debug("Setup CPU Interface\r\n"); c3_cpu_setup(ctrl.d0f2); - ddr_ram_setup(); if (bist == 0) { @@ -158,3 +153,4 @@ static void main(unsigned long bist) print_spew("Leaving romstage.c:main()\r\n"); } + diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 8d3978415f..1b5e9e21b8 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -126,3 +123,4 @@ static void main(unsigned long bist) } #endif } + diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0b24259502..9bfaefffc4 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -83,3 +80,4 @@ static void main(unsigned long bist) /* ram_check(0, 640 * 1024); */ } + diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 52b93fdc22..168e496f22 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -19,9 +19,6 @@ * MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -132,3 +129,4 @@ static void main(unsigned long bist) void amd64_main(unsigned long bist) { main(bist); } + diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index c9730b0ad7..fecbe486d1 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -88,7 +85,6 @@ static const struct msrinit msr_table[] = {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF }; - static void msr_init(void) { int i; @@ -135,3 +131,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + |