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author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2017-09-26 13:54:12 +0530 |
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committer | Furquan Shaikh <furquan@google.com> | 2017-10-03 20:25:39 +0000 |
commit | 868b3761c71b2d106509c6cb8164f5a0472682a2 (patch) | |
tree | f369a1fdba958df40773a6fa18e52eb241da0ec2 /src | |
parent | ed3e6b8b946e0c5fbc417551750da67c284eaf8b (diff) | |
download | coreboot-868b3761c71b2d106509c6cb8164f5a0472682a2.tar.xz |
mainboard/google/soraka: Reduce Wacom resume time
Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.
BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.
Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 6d4e8a5665..f6948d953b 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -281,7 +281,6 @@ chip soc/intel/skylake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" - register "generic.reset_delay_ms" = "110" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "1" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" |