haswell: add multipurpose SMM memory region

The SMM region is available for multipurpose use before the SMM
handler is relocated. Provide a configurable sized region in the
TSEG for use before the SMM handler is relocated. This feature is
implemented by making the reserved size a Kconfig option. Also
make the IED region a Kconfig option as well. Lastly add some sanity
checking on the Kconfig options.

Change-Id: Idd7fccf925a8787146906ac766b7878845c75935
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2804
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

4 files changed, 33 insertions, 2 deletions

diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 95d0b18ff2..b49795dd91 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -29,6 +29,14 @@ config SMM_TSEG_SIZE
 	hex
 	default 0x800000
 
+config IED_REGION_SIZE
+	hex
+	default 0x400000
+
+config SMM_RESERVED_SIZE
+	hex
+	default 0x100000
+
 config MICROCODE_INCLUDE_PATH
 	string
 	default "src/cpu/intel/haswell"
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index a510e7de58..3a5ebe65ae 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -100,6 +100,26 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
+/* Region of SMM space is reserved for multipurpose use. It falls below
+ * the IED region and above the SMM handler. */
+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
+#define RESERVED_SMM_OFFSET \
+	(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
+
+/* Sanity check config options. */
+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
+#endif
+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
+#endif
+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
+#endif
+#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
+# error "CONFIG_IED_REGION_SIZE is not a power of 2"
+#endif
+
 #ifndef __ROMCC__
 
 #if defined(__PRE_RAM__)
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 2a322a7f9a..65ac36388f 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -258,6 +258,9 @@ static void fill_in_relocation_params(device_t dev,
 	params->ied_base = tsegmb + params->smram_size;
 	params->ied_size = tseg_size - params->smram_size;
 
+	/* Adjust available SMM handler memory size. */
+	params->smram_size -= RESERVED_SMM_SIZE;
+
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */
 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
 	params->smrr_base.hi = 0;
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 3a1803858a..ba88722452 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -43,8 +43,8 @@
 #define IVB_STEP_K0	(BASE_REV_IVB + 5)
 #define IVB_STEP_D0	(BASE_REV_IVB + 6)
 
-/* Intel Enhanced Debug region must be 4MB */
-#define IED_SIZE	0x400000
+/* Intel Enhanced Debug region */
+#define IED_SIZE	CONFIG_IED_REGION_SIZE
 
 /* Northbridge BARs */
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */