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authorMichael Niewöhner <foss@mniewoehner.de>2019-11-08 22:02:02 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-11 10:25:40 +0000
commit8f22136c051f04ef0102fd468ba01a0f10f1a37c (patch)
tree4ce6607d13938b092be7d95e5ea945f18a04d68f /src
parentbc2f9a30f3a61e3d02baf7abcc5440407035f354 (diff)
downloadcoreboot-8f22136c051f04ef0102fd468ba01a0f10f1a37c.tar.xz
include/device: add pci mmio cfg address helpers
Add helpers for getting the pci mmio cfg address for a register. Change-Id: Ie6fe22cacc7241a51d47cbe9fc64f30fa49d5a80 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/include/device/pci_mmio_cfg.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h
index e3c5fe4873..8f26ff29b0 100644
--- a/src/include/device/pci_mmio_cfg.h
+++ b/src/include/device/pci_mmio_cfg.h
@@ -86,6 +86,24 @@ void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value;
}
+static __always_inline
+uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg)
+{
+ return (uint8_t *)&pcicfg(dev)->reg8[reg];
+}
+
+static __always_inline
+uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg)
+{
+ return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)];
+}
+
+static __always_inline
+uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg)
+{
+ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
+}
+
#endif /* !defined(__ROMCC__) */
#if CONFIG(MMCONF_SUPPORT)