diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-16 18:38:54 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-26 06:03:00 +0000 |
| commit | 97a09454d25bc19b80ae990743602ba0f943a9c0 (patch) | |
| tree | bc00fd1beb7fe7800448195ae9943cf6a33a5951 /src | |
| parent | f61ffcf9a489fa5d971f8584450be0869e6ca78d (diff) | |
| download | coreboot-97a09454d25bc19b80ae990743602ba0f943a9c0.tar.xz | |
soc/intel/skylake: Move DMI lock down config after resource allocation
This patch to ensures that coreboot is performing DMI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence BIOS Interface lock down through Sideband
access has been moved right after pci resource allocation is done,
so that BILD lock down is getting executed along with LPC and SPI
BIOS interface lockdown settings before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure DMI register offset 0x274c bit 0 is set.
Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/lockdown.c | 14 |
2 files changed, 14 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index c38ac632c5..335435ad9d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -35,8 +35,6 @@ #include <soc/systemagent.h> #include <stdlib.h> -#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) #define PSF_BASE_ADDRESS 0xA00 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) @@ -168,9 +166,6 @@ static void soc_lockdown(void) /* Bios Interface Lock */ fast_spi_set_bios_interface_lock_down(); - /* GCS reg of DMI */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); - /* Bios Lock */ fast_spi_set_lock_enable(); } diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index f2a9e8b19f..5bbf546de0 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -16,11 +16,16 @@ #include <arch/io.h> #include <bootstate.h> #include <chip.h> +#include <intelblocks/pcr.h> #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <soc/pm.h> #include <string.h> +#define PCR_DMI_GCS 0x274C +#define PCR_DMI_GCS_BILD (1 << 0) + static void lpc_lockdown_config(void) { static struct soc_intel_skylake_config *config; @@ -55,11 +60,20 @@ static void pmc_lockdown_config(void) write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); } +static void dmi_lockdown_config(void) +{ + /* GCS reg of DMI */ + pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); +} + static void platform_lockdown_config(void *unused) { /* LPC lock down configuration */ lpc_lockdown_config(); + /* DMI lock down configuration */ + dmi_lockdown_config(); + /* PMC lock down configuration */ pmc_lockdown_config(); } |