diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-07-28 14:20:58 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-08-01 00:52:23 +0200 |
| commit | aaaef061792f7904d75f401e1de376311d6cdd0b (patch) | |
| tree | 6ef094d7d8102a4b8748477774c51df17776a358 /src | |
| parent | 0d7f133c38673af2dae06988d418606d7f5628ac (diff) | |
| download | coreboot-aaaef061792f7904d75f401e1de376311d6cdd0b.tar.xz | |
fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1
The GPIO_NC setting sets up the gpio as a no-connect - sets it as an
input, and pulls it high. It makes an assumption that the GPIO
function is muxing function 0. There are a few GPIOs that are on
function 1 instead:
* GPIO_S0_SC[092-93]
* GPIO_S5[11-21]
For these GPIOs, use the GPIO_NC1 setting instead of GPIO_NC.
Change-Id: Iac6790b40e87ad4ac9a3b265a8e10662186c1201
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6428
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/gpio.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index 4c9e8a821d..957b0defd8 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -156,8 +156,8 @@ #define PAD_VAL_DEFAULT PAD_VAL_INPUT /* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ +#define GPIO_INPUT_PU_10K(_func) \ + { .pad_conf0 = PAD_FUNC##_func | PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_MMIO, \ @@ -265,9 +265,10 @@ /* Common default GPIO settings */ #define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_10K +#define GPIO_INPUT_PU GPIO_INPUT_PU_10K(0) #define GPIO_INPUT_PD GPIO_INPUT_PD_10K -#define GPIO_NC GPIO_INPUT_PU_10K +#define GPIO_NC GPIO_INPUT_PU_10K(0) +#define GPIO_NC1 GPIO_INPUT_PU_10K(1) #define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */ |