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authorDuncan Laurie <dlaurie@chromium.org>2015-12-10 01:03:21 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-18 12:11:23 +0100
commitae34cae4fe12d9e6b5a70b577d181bb813aa3840 (patch)
treefaf05445a76e8bb325baf6d06342ce868ca10665 /src
parentddd9f1a5a65db7a461ffb6576ca45acf56c2b000 (diff)
downloadcoreboot-ae34cae4fe12d9e6b5a70b577d181bb813aa3840.tar.xz
google/glados: Add pull-ups on LPC address lines and setup PCH_WP early
Copy changes from chell to add 20K pull-up to LPC address lines and setup the PCH_WP signal early so it is set correctly in VBNV. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4 Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317244 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12982 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/glados/gpio.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index cd7a93677f..5ea6691ba7 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -57,10 +57,10 @@
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
-/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
-/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
-/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
/* PIRQA# */ /* GPP_A7 */