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| author | Kevin Cody-Little <kcodyjr@gmail.com> | 2018-05-09 14:14:59 -0400 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-05-13 10:16:24 +0000 |
| commit | c97b5af898d21dbc089d336ccd863ccfd6bd965a (patch) | |
| tree | e579ad5680e8f54959480d498cc83dfe1861868e /src | |
| parent | d4fec689fd125c92388dc1dd4775ea21d0e1e447 (diff) | |
| download | coreboot-c97b5af898d21dbc089d336ccd863ccfd6bd965a.tar.xz | |
drivers/pc80/tpm: get ioport from pnp records
Had 0x2e hardcoded, which is often the SuperIO chip. Instead,
pull the port from the PNP tree generated from devicetree.cb,
where either 0x4e or 0x2e will be specified.
Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/pc80/tpm/tis.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 714b7e5ed0..3549173210 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -904,11 +904,13 @@ static void lpc_tpm_fill_ssdt(struct device *dev) else acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_OFF); + u16 port = dev->path.pnp.port; + /* Resources */ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_write_mem32fixed(1, CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000); - acpigen_write_io16(0x2e, 0x2e, 1, 2, 1); + acpigen_write_io16(port, port, 1, 2, 1); if (CONFIG_TPM_PIRQ) { /* |