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| author | Andrey Petrov <anpetrov@fb.com> | 2020-01-28 10:51:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-18 20:12:14 +0000 |
| commit | d1f7c6f2867ad7ede4af36ed42860a206538c550 (patch) | |
| tree | 06d617a2974aa15c64dd013bba7cd990580bb483 /src | |
| parent | 286b07ca33dfc827463d1b701dc3cb2457f13bf4 (diff) | |
| download | coreboot-d1f7c6f2867ad7ede4af36ed42860a206538c550.tar.xz | |
cpu: Allow to configure microcode at pre-defined address
FSP-T takes microcode pointer and location parameters, and FSP-T is
invoked before CAR is set-up and before memory is trained. So it is not
possible to modify supplied microcode pointer in runtime. Because of
that we have to hardcode the pointer in bootblock.
Also, current FSP-T on Xeons require microcode (it is not optional).
Reasons for that are currently unclear and are being investigated.
However for the present time we need to be able to add microcode at a
certain offset so FSP-T can be used.
TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board
Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 4b5d67b908..0289be0297 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -60,3 +60,7 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode cpu_microcode_blob.bin-align := 16 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +endif |