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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-17 18:48:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:35:15 +0000 |
| commit | dce635977381ff293f7f74c5cdfae142f36412d8 (patch) | |
| tree | 1c77a729b0c09a7111de04d0187531cd45c96d35 /src | |
| parent | 1c6ea92e6fcee21aa01a20500594a09ab14caa74 (diff) | |
| download | coreboot-dce635977381ff293f7f74c5cdfae142f36412d8.tar.xz | |
soc/intel/cannonlake: lockdown: lock global reset
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.
Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/lockdown.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index ba68aa385c..c556839d18 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> +#include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pm.h> @@ -60,6 +61,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); |