lib: provide clearer devicetree semantics

The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:

1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST

The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.

Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

23 files changed, 77 insertions, 68 deletions

diff --git a/src/device/device_simple.c b/src/device/device_simple.c
index 828e99b75e..2cacb4a9ac 100644
--- a/src/device/device_simple.c
+++ b/src/device/device_simple.c
@@ -24,7 +24,7 @@
 #include <device/resource.h>
 
 /** Linked list of ALL devices */
-ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root;
+DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root;
 
 /**
  * Given a PCI bus and a devfn number, find the device structure.
@@ -33,10 +33,10 @@ ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root;
  * @param devfn A device/function number.
  * @return Pointer to the device structure (if found), 0 otherwise.
  */
-ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus,
+DEVTREE_CONST struct device *dev_find_slot(unsigned int bus,
 						unsigned int devfn)
 {
-	ROMSTAGE_CONST struct device *dev, *result;
+	DEVTREE_CONST struct device *dev, *result;
 
 	result = 0;
 	for (dev = all_devices; dev; dev = dev->next) {
@@ -56,10 +56,10 @@ ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus,
  * @param previous_dev A pointer to a PCI device structure.
  * @return Pointer to the next device structure (if found), 0 otherwise.
  */
-ROMSTAGE_CONST struct device *dev_find_next_pci_device(
-		ROMSTAGE_CONST struct device *previous_dev)
+DEVTREE_CONST struct device *dev_find_next_pci_device(
+		DEVTREE_CONST struct device *previous_dev)
 {
-	ROMSTAGE_CONST struct device *dev, *result;
+	DEVTREE_CONST struct device *dev, *result;
 
 	if (previous_dev == NULL)
 		previous_dev = all_devices;
@@ -81,10 +81,10 @@ ROMSTAGE_CONST struct device *dev_find_next_pci_device(
  * @param addr A device number.
  * @return Pointer to the device structure (if found), 0 otherwise.
  */
-ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
+DEVTREE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
 							unsigned int addr)
 {
-	ROMSTAGE_CONST struct device *dev, *result;
+	DEVTREE_CONST struct device *dev, *result;
 
 	result = 0;
 	for (dev = all_devices; dev; dev = dev->next) {
@@ -105,9 +105,9 @@ ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
  * @param device Logical device number.
  * @return Pointer to the device structure (if found), 0 otherwise.
  */
-ROMSTAGE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device)
+DEVTREE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device)
 {
-	ROMSTAGE_CONST struct device *dev;
+	DEVTREE_CONST struct device *dev;
 
 	for (dev = all_devices; dev; dev = dev->next) {
 		if ((dev->path.type == DEVICE_PATH_PNP) &&
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index f44e3e8ba9..42f7966e03 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -25,7 +25,7 @@
 #include <device/pci_def.h>
 
 static unsigned int oxpcie_present CAR_GLOBAL;
-static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
+static DEVTREE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
 
 int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
 {
diff --git a/src/include/device/device.h b/src/include/device/device.h
index bb0d0ca8b8..7b4fce36ea 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -84,9 +84,9 @@ static inline void device_noop(struct device *dev) {}
 
 struct bus {
 
-	ROMSTAGE_CONST struct device *dev;	/* This bridge device */
-	ROMSTAGE_CONST struct device *children;	/* devices behind this bridge */
-	ROMSTAGE_CONST struct bus *next;    /* The next bridge on this device */
+	DEVTREE_CONST struct device *dev;	/* This bridge device */
+	DEVTREE_CONST struct device *children;	/* devices behind this bridge */
+	DEVTREE_CONST struct bus *next;    /* The next bridge on this device */
 	unsigned int	bridge_ctrl;	/* Bridge control register */
 	uint16_t	bridge_cmd;		/* Bridge command register */
 	unsigned char	link_num;	/* The index of this link */
@@ -113,12 +113,12 @@ struct pci_irq_info {
 };
 
 struct device {
-	ROMSTAGE_CONST struct bus *bus;	/* bus this device is on, for bridge
+	DEVTREE_CONST struct bus *bus;	/* bus this device is on, for bridge
 					 * devices, it is the up stream bus */
 
-	ROMSTAGE_CONST struct device *sibling;	/* next device on this bus */
+	DEVTREE_CONST struct device *sibling;	/* next device on this bus */
 
-	ROMSTAGE_CONST struct device *next;	/* chain of all devices */
+	DEVTREE_CONST struct device *next;	/* chain of all devices */
 
 	struct device_path path;
 	unsigned int	vendor;
@@ -134,26 +134,26 @@ struct device {
 	u8 command;
 
 	/* Base registers for this device. I/O, MEM and Expansion ROM */
-	ROMSTAGE_CONST struct resource *resource_list;
+	DEVTREE_CONST struct resource *resource_list;
 
 	/* links are (downstream) buses attached to the device, usually a leaf
 	 * device with no children has 0 buses attached and a bridge has 1 bus
 	 */
-	ROMSTAGE_CONST struct bus *link_list;
+	DEVTREE_CONST struct bus *link_list;
 
 	struct device_operations *ops;
-#ifndef __PRE_RAM__
+#if !DEVTREE_EARLY
 	struct chip_operations *chip_ops;
 	const char *name;
 #endif
-	ROMSTAGE_CONST void *chip_info;
+	DEVTREE_CONST void *chip_info;
 };
 
 /**
  * This is the root of the device tree. The device tree is defined in the
  * static.c file and is generated by the config tool at compile time.
  */
-extern ROMSTAGE_CONST struct device	dev_root;
+extern DEVTREE_CONST struct device	dev_root;
 
 #ifndef __SIMPLE_DEVICE__
 
@@ -272,13 +272,13 @@ u32 find_pci_tolm(struct bus *bus);
 
 #else /* vv __SIMPLE_DEVICE__ vv */
 
-ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus,
+DEVTREE_CONST struct device *dev_find_slot(unsigned int bus,
 						unsigned int devfn);
-ROMSTAGE_CONST struct device *dev_find_next_pci_device(
-				ROMSTAGE_CONST struct device *previous_dev);
-ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
+DEVTREE_CONST struct device *dev_find_next_pci_device(
+				DEVTREE_CONST struct device *previous_dev);
+DEVTREE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
 							unsigned int addr);
-ROMSTAGE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device);
+DEVTREE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device);
 
 #endif
 
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index d794fb21e7..eefaf96e28 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -42,7 +42,7 @@ struct resource {
 	resource_t base;	/* Base address of the resource */
 	resource_t size;	/* Size of the resource */
 	resource_t limit;	/* Largest valid value base + size -1 */
-	ROMSTAGE_CONST struct resource *next;	/* Next resource in the list */
+	DEVTREE_CONST struct resource *next;	/* Next resource in the list */
 	unsigned long flags;	/* Descriptions of the kind of resource */
 	unsigned long index;	/* Bus specific per device resource id */
 	unsigned char align;	/* Required alignment (log 2) of the resource */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index d0308d2580..af63196697 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -2,6 +2,7 @@
 #define STDDEF_H
 
 #include <commonlib/helpers.h>
+#include <rules.h>
 
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
@@ -21,10 +22,18 @@ typedef unsigned int wint_t;
 
 #define NULL ((void *)0)
 
-#ifdef __PRE_RAM__
-#define ROMSTAGE_CONST const
+/* The devicetree data structures are only mutable in ramstage. All other
+   stages have a constant devicetree. */
+#if !ENV_RAMSTAGE
+#define DEVTREE_EARLY 1
 #else
-#define ROMSTAGE_CONST
+#define DEVTREE_EARLY 0
+#endif
+
+#if DEVTREE_EARLY
+#define DEVTREE_CONST const
+#else
+#define DEVTREE_CONST
 #endif
 
 /* Work around non-writable data segment in execute-in-place romstage on x86. */
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index 0fe8bd5ec7..e5eed05679 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -109,8 +109,8 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	int spdAddress;
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
 
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
 	UINT8 spdAddrLookup_rev_F [2][2][4]= {
 		{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
 		{ {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c
index f8c5b02f46..d992414bb5 100644
--- a/src/northbridge/amd/agesa/family14/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.c
@@ -34,11 +34,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	UINT8 spdAddress;
 
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	if (dev == NULL)
 		return AGESA_ERROR;
 
-	ROMSTAGE_CONST struct northbridge_amd_agesa_family14_config *config = dev->chip_info;
+	DEVTREE_CONST struct northbridge_amd_agesa_family14_config *config = dev->chip_info;
 	if (config == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c
index de75701a8a..3b1220201a 100644
--- a/src/northbridge/amd/agesa/family15/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15/dimmSpd.c
@@ -34,11 +34,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	UINT8 spdAddress;
 
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	if (dev == NULL)
 		return AGESA_ERROR;
 
-	ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = dev->chip_info;
+	DEVTREE_CONST struct northbridge_amd_agesa_family15_config *config = dev->chip_info;
 	if (config == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family15rl/dimmSpd.c b/src/northbridge/amd/agesa/family15rl/dimmSpd.c
index 2c1de73104..7d0f2a1c9c 100644
--- a/src/northbridge/amd/agesa/family15rl/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15rl/dimmSpd.c
@@ -34,11 +34,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	UINT8 spdAddress;
 
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	if (dev == NULL)
 		return AGESA_ERROR;
 
-	ROMSTAGE_CONST struct northbridge_amd_agesa_family15rl_config *config = dev->chip_info;
+	DEVTREE_CONST struct northbridge_amd_agesa_family15rl_config *config = dev->chip_info;
 	if (config == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
index de45870601..6273843dbb 100644
--- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
@@ -33,11 +33,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	UINT8 spdAddress;
 
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	if (dev == NULL)
 		return AGESA_ERROR;
 
-	ROMSTAGE_CONST struct northbridge_amd_agesa_family15tn_config *config = dev->chip_info;
+	DEVTREE_CONST struct northbridge_amd_agesa_family15tn_config *config = dev->chip_info;
 	if (config == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
index 82d67d5038..a2319bc110 100644
--- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
@@ -33,11 +33,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	UINT8 spdAddress;
 
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	if (dev == NULL)
 		return AGESA_ERROR;
 
-	ROMSTAGE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
+	DEVTREE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
 	if (config == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c
index eba0449ee1..31f6f59a70 100644
--- a/src/northbridge/amd/pi/00630F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c
@@ -29,8 +29,8 @@
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00630F01_config *config = dev->chip_info;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct northbridge_amd_pi_00630F01_config *config = dev->chip_info;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c
index 5c81f36f2c..6b773bc7fe 100644
--- a/src/northbridge/amd/pi/00660F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c
@@ -27,8 +27,8 @@
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00670F00/dimmSpd.c b/src/northbridge/amd/pi/00670F00/dimmSpd.c
index e0d67d7fb6..42512ce902 100644
--- a/src/northbridge/amd/pi/00670F00/dimmSpd.c
+++ b/src/northbridge/amd/pi/00670F00/dimmSpd.c
@@ -27,8 +27,8 @@
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c
index 9726042879..424bff16e2 100644
--- a/src/northbridge/amd/pi/00730F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c
@@ -29,8 +29,8 @@
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index 6a33eda202..ed79f45e8d 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -55,8 +55,8 @@ typedef struct northbridge_intel_fsp_rangeley_config config_t;
  */
 static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
 {
-	ROMSTAGE_CONST struct device *dev;
-	ROMSTAGE_CONST config_t *config;
+	DEVTREE_CONST struct device *dev;
+	DEVTREE_CONST config_t *config;
 	printk(BIOS_DEBUG, "Configure Default UPD Data\n");
 
 	dev = dev_find_slot(0, SOC_DEV_FUNC);
diff --git a/src/soc/intel/apollolake/i2c_early.c b/src/soc/intel/apollolake/i2c_early.c
index 4eb2b86042..871c7621a9 100644
--- a/src/soc/intel/apollolake/i2c_early.c
+++ b/src/soc/intel/apollolake/i2c_early.c
@@ -28,8 +28,8 @@
 
 static int i2c_early_init_bus(unsigned int bus)
 {
-	ROMSTAGE_CONST struct soc_intel_apollolake_config *config;
-	ROMSTAGE_CONST struct device *tree_dev;
+	DEVTREE_CONST struct soc_intel_apollolake_config *config;
+	DEVTREE_CONST struct device *tree_dev;
 	pci_devfn_t dev;
 	int devfn;
 	uintptr_t base;
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 9e57b28abe..9999913bb3 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -502,10 +502,10 @@ void pmc_gpe_init(void)
 	uint32_t gpio_cfg = 0;
 	uint32_t gpio_cfg_reg;
 	uint8_t dw1, dw2, dw3;
-	ROMSTAGE_CONST struct soc_intel_apollolake_config *config;
+	DEVTREE_CONST struct soc_intel_apollolake_config *config;
 
 	/* Look up the device in devicetree */
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 74b94752b1..51e8ef54e1 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -107,13 +107,13 @@
 #if defined(__SIMPLE_DEVICE__)
 
 static uintptr_t gspi_get_base_addr(int devfn,
-				ROMSTAGE_CONST struct device *dev)
+				DEVTREE_CONST struct device *dev)
 {
 	pci_devfn_t pci_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
 	return ALIGN_DOWN(pci_read_config32(pci_dev, PCI_BASE_ADDRESS_0), 16);
 }
 
-static void gspi_set_base_addr(int devfn, ROMSTAGE_CONST struct device *dev,
+static void gspi_set_base_addr(int devfn, DEVTREE_CONST struct device *dev,
 				uintptr_t base)
 {
 	pci_devfn_t pci_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
@@ -172,7 +172,7 @@ static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base)
 static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus)
 {
 	uintptr_t bus_base, gspi_base_addr;
-	ROMSTAGE_CONST struct device *dev;
+	DEVTREE_CONST struct device *dev;
 	int devfn = gspi_soc_bus_to_devfn(gspi_bus);
 
 	if (devfn < 0)
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 108568276c..c7c984c5e7 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -82,8 +82,8 @@ static const char *emmc_mode_strings[] = {
  */
 static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
 {
-	ROMSTAGE_CONST struct device *dev;
-	ROMSTAGE_CONST config_t *config;
+	DEVTREE_CONST struct device *dev;
+	DEVTREE_CONST config_t *config;
 	printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
 
 	dev = dev_find_slot(0, SOC_DEV_FUNC);
diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c
index 59cb5c8bc2..f8859a4607 100644
--- a/src/soc/intel/skylake/bootblock/i2c.c
+++ b/src/soc/intel/skylake/bootblock/i2c.c
@@ -44,8 +44,8 @@ uintptr_t lpss_i2c_base_address(unsigned int bus)
 
 static void i2c_early_init_bus(unsigned int bus)
 {
-	ROMSTAGE_CONST struct soc_intel_skylake_config *config;
-	ROMSTAGE_CONST struct device *tree_dev;
+	DEVTREE_CONST struct soc_intel_skylake_config *config;
+	DEVTREE_CONST struct device *tree_dev;
 	pci_devfn_t dev;
 	int devfn;
 	uintptr_t base;
diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c
index e04ae93b52..eef5433826 100644
--- a/src/soc/intel/skylake/gspi.c
+++ b/src/soc/intel/skylake/gspi.c
@@ -22,9 +22,9 @@
 
 const struct gspi_cfg *gspi_get_soc_cfg(void)
 {
-	ROMSTAGE_CONST struct soc_intel_skylake_config *config;
+	DEVTREE_CONST struct soc_intel_skylake_config *config;
 	int devfn = SA_DEVFN_ROOT;
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, devfn);
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
 
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 209bb902e8..9b38531129 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -484,8 +484,8 @@ void poweroff(void)
 
 void pmc_gpe_init(void)
 {
-	ROMSTAGE_CONST struct soc_intel_skylake_config *config;
-	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+	DEVTREE_CONST struct soc_intel_skylake_config *config;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
 	uint8_t *pmc_regs;
 	uint32_t gpio_cfg;
 	uint32_t gpio_cfg_reg;