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| author | Frans Hendriks <fhendriks@eltan.com> | 2019-10-02 10:16:26 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-10-03 14:05:53 +0000 |
| commit | f26a1985bf2d5bea1b345cd306443e0ebb77e27a (patch) | |
| tree | 6afbdf747defac179e3ffae5632e18fa9b631ab9 /src | |
| parent | 0b20b83b7da32fc96f41ca7fe92c920d36a05b05 (diff) | |
| download | coreboot-f26a1985bf2d5bea1b345cd306443e0ebb77e27a.tar.xz | |
soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB
Add defines to have some more readable code for devcietree.cb.
BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 747b941f55..9f790dc140 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,6 +32,11 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 +#define IGD_MEMSIZE_32MB 0x01 +#define IGD_MEMSIZE_64MB 0x02 +#define IGD_MEMSIZE_96MB 0x03 +#define IGD_MEMSIZE_128MB 0x04 + enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, |