Rename almost all occurences of LinuxBIOS to coreboot.

Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

241 files changed, 1204 insertions, 1204 deletions

diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb
index 09eb1a22b8..ec1dd1ee0d 100644
--- a/src/arch/i386/Config.lb
+++ b/src/arch/i386/Config.lb
@@ -22,12 +22,12 @@ else
 end
 
 makerule all
-	depends	"linuxbios.rom"
+	depends	"coreboot.rom"
 end
 
 makerule floppy 
 	depends	"all" 
-	action	"mcopy -o linuxbios.rom a:"
+	action	"mcopy -o coreboot.rom a:"
 end
 
 makerule nrv2b 
@@ -55,7 +55,7 @@ end
 # this one example shows the mess that has occurred. People are now mixing
 # conditional if in the make style with if in the config language style. 
 # The -1 is linux standard. 
-# I don't much like it but it is the mode nowadays. So linuxbios will change
+# I don't much like it but it is the mode nowadays. So coreboot will change
 # what a mess. -- RGM
 # catch the case where there is no compression
 makedefine PAYLOAD-1:=payload
@@ -70,16 +70,16 @@ if CONFIG_PRECOMPRESSED_PAYLOAD
 end
 
 if USE_FAILOVER_IMAGE
-	makedefine LINUXBIOS_APC:=
-	makedefine LINUXBIOS_RAM_ROM:=
+	makedefine COREBOOT_APC:=
+	makedefine COREBOOT_RAM_ROM:=
 
-	makerule linuxbios.rom 
-		depends	"linuxbios.strip" 
+	makerule coreboot.rom 
+		depends	"coreboot.strip" 
 		action "cp $< $@"
 	end
 else
-	makerule linuxbios.rom 
-		depends	"linuxbios.strip buildrom $(PAYLOAD-1)" 
+	makerule coreboot.rom 
+		depends	"coreboot.strip buildrom $(PAYLOAD-1)" 
 		action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
 	end
 end
@@ -98,10 +98,10 @@ if CONFIG_USE_INIT
 	        action  "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
 	end
 
-        makerule linuxbios   
-		depends	"crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
+        makerule coreboot   
+		depends	"crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
 		action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
-		action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
+		action	"$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
         end
 
 end
diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c
index b437e85229..46e3291641 100644
--- a/src/arch/i386/boot/acpi.c
+++ b/src/arch/i386/boot/acpi.c
@@ -1,5 +1,5 @@
 /*
- * LinuxBIOS ACPI Table support
+ * coreboot ACPI Table support
  * written by Stefan Reinauer <stepan@openbios.org>
  *  (C) 2004 SUSE LINUX AG
  *  (C) 2005 Stefan Reinauer
diff --git a/src/arch/i386/boot/boot.c b/src/arch/i386/boot/boot.c
index 84c71da800..edba2d1c3d 100644
--- a/src/arch/i386/boot/boot.c
+++ b/src/arch/i386/boot/boot.c
@@ -113,8 +113,8 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
 		"	addl	12(%%esp), %%eax\n\t"
 		"	addl	 8(%%esp), %%eax\n\t"
 		"	movl	%%eax, 20(%%esp)\n\t"
-		/* Place a copy of linuxBIOS in it's new location */
-		/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
+		/* Place a copy of coreboot in it's new location */
+		/* Move ``longs'' the coreboot size is 4 byte aligned */
 		"	movl	12(%%esp), %%edi\n\t"
 		"	addl	 8(%%esp), %%edi\n\t"
 		"	movl	16(%%esp), %%esi\n\t"
@@ -122,16 +122,16 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
 		"	shrl	$2, %%ecx\n\t"
 		"	rep	movsl\n\t"
 
-		/* Adjust the stack pointer to point into the new linuxBIOS image */
+		/* Adjust the stack pointer to point into the new coreboot image */
 		"	addl	20(%%esp), %%esp\n\t"
-		/* Adjust the instruction pointer to point into the new linuxBIOS image */
+		/* Adjust the instruction pointer to point into the new coreboot image */
 		"	movl	$1f, %%eax\n\t"
 		"	addl	20(%%esp), %%eax\n\t"
 		"	jmp	*%%eax\n\t"
 		"1:	\n\t"
 
-		/* Copy the linuxBIOS bounce buffer over linuxBIOS */
-		/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
+		/* Copy the coreboot bounce buffer over coreboot */
+		/* Move ``longs'' the coreboot size is 4 byte aligned */
 		"	movl	16(%%esp), %%edi\n\t"
 		"	movl	12(%%esp), %%esi\n\t"
 		"	movl	 8(%%esp), %%ecx\n\t"
@@ -147,8 +147,8 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
 		"	cli	\n\t"
 		"	cld	\n\t"
 
-		/* Copy the saved copy of linuxBIOS where linuxBIOS runs */
-		/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
+		/* Copy the saved copy of coreboot where coreboot runs */
+		/* Move ``longs'' the coreboot size is 4 byte aligned */
 		"	movl	16(%%esp), %%edi\n\t"
 		"	movl	12(%%esp), %%esi\n\t"
 		"	addl	 8(%%esp), %%esi\n\t"
@@ -156,10 +156,10 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
 		"	shrl	$2, %%ecx\n\t"
 		"	rep	movsl\n\t"
 
-		/* Adjust the stack pointer to point into the old linuxBIOS image */
+		/* Adjust the stack pointer to point into the old coreboot image */
 		"	subl	20(%%esp), %%esp\n\t"
 
-		/* Adjust the instruction pointer to point into the old linuxBIOS image */
+		/* Adjust the instruction pointer to point into the old coreboot image */
 		"	movl	$1f, %%eax\n\t"
 		"	subl	20(%%esp), %%eax\n\t"
 		"	jmp	*%%eax\n\t"
diff --git a/src/arch/i386/boot/linuxbios_table.c b/src/arch/i386/boot/linuxbios_table.c
index e32d2467a9..0dbdce36d6 100644
--- a/src/arch/i386/boot/linuxbios_table.c
+++ b/src/arch/i386/boot/linuxbios_table.c
@@ -122,16 +122,16 @@ void lb_strings(struct lb_header *header)
 		uint32_t tag;
 		const char *string;
 	} strings[] = {
-		{ LB_TAG_VERSION,        linuxbios_version,        },
-		{ LB_TAG_EXTRA_VERSION,  linuxbios_extra_version,  },
-		{ LB_TAG_BUILD,          linuxbios_build,          },
-		{ LB_TAG_COMPILE_TIME,   linuxbios_compile_time,   },
-		{ LB_TAG_COMPILE_BY,     linuxbios_compile_by,     },
-		{ LB_TAG_COMPILE_HOST,   linuxbios_compile_host,   },
-		{ LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
-		{ LB_TAG_COMPILER,       linuxbios_compiler,       },
-		{ LB_TAG_LINKER,         linuxbios_linker,         },
-		{ LB_TAG_ASSEMBLER,      linuxbios_assembler,      },
+		{ LB_TAG_VERSION,        coreboot_version,        },
+		{ LB_TAG_EXTRA_VERSION,  coreboot_extra_version,  },
+		{ LB_TAG_BUILD,          coreboot_build,          },
+		{ LB_TAG_COMPILE_TIME,   coreboot_compile_time,   },
+		{ LB_TAG_COMPILE_BY,     coreboot_compile_by,     },
+		{ LB_TAG_COMPILE_HOST,   coreboot_compile_host,   },
+		{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
+		{ LB_TAG_COMPILER,       coreboot_compiler,       },
+		{ LB_TAG_LINKER,         coreboot_linker,         },
+		{ LB_TAG_ASSEMBLER,      coreboot_assembler,      },
 	};
 	unsigned int i;
 	for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
@@ -201,7 +201,7 @@ unsigned long lb_table_fini(struct lb_header *head)
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk_debug("Wrote linuxbios table at: %p - %p  checksum %lx\n",
+	printk_debug("Wrote coreboot table at: %p - %p  checksum %lx\n",
 		head, rec, head->table_checksum);
 	return (unsigned long)rec;
 }
@@ -315,8 +315,8 @@ static void lb_add_memory_range(struct lb_memory *mem,
 	lb_cleanup_memory_ranges(mem);
 }
 
-/* Routines to extract part so the linuxBIOS table or 
- * information from the linuxBIOS table after we have written it.
+/* Routines to extract part so the coreboot table or 
+ * information from the coreboot table after we have written it.
  * Currently get_lb_mem relies on a global we can change the
  * implementaiton.
  */
@@ -348,7 +348,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
 	return mem;
 }
 
-unsigned long write_linuxbios_table( 
+unsigned long write_coreboot_table( 
 	unsigned long low_table_start, unsigned long low_table_end, 
 	unsigned long rom_table_start, unsigned long rom_table_end)
 {
@@ -383,7 +383,7 @@ unsigned long write_linuxbios_table(
 		rec_dest = lb_new_record(head);
 		rec_src = (struct lb_record *)(void *)&option_table;
 		memcpy(rec_dest,  rec_src, rec_src->size);
-		/* Create cmos checksum entry in linuxbios table */
+		/* Create cmos checksum entry in coreboot table */
 		lb_cmos_checksum(head);
 	}
 #endif
@@ -401,9 +401,9 @@ unsigned long write_linuxbios_table(
 
 	/* Note:
 	 * I assume that there is always memory at immediately after
-	 * the low_table_end.  This means that after I setup the linuxbios table.
+	 * the low_table_end.  This means that after I setup the coreboot table.
 	 * I can trivially fixup the reserved memory ranges to hold the correct
-	 * size of the linuxbios table.
+	 * size of the coreboot table.
 	 */
 
 	/* Record our motheboard */
diff --git a/src/arch/i386/boot/linuxbios_table.h b/src/arch/i386/boot/linuxbios_table.h
index 41ac37a8de..7944791de2 100644
--- a/src/arch/i386/boot/linuxbios_table.h
+++ b/src/arch/i386/boot/linuxbios_table.h
@@ -1,10 +1,10 @@
-#ifndef LINUXBIOS_TABLE_H
-#define LINUXBIOS_TABLE_H
+#ifndef COREBOOT_TABLE_H
+#define COREBOOT_TABLE_H
 
 #include <boot/linuxbios_tables.h>
 
-/* This file holds function prototypes for building the linuxbios table. */
-unsigned long write_linuxbios_table(
+/* This file holds function prototypes for building the coreboot table. */
+unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end);
 
@@ -19,11 +19,11 @@ void lb_memory_range(struct lb_memory *mem,
 struct lb_mainboard *lb_mainboard(struct lb_header *header);
 unsigned long lb_table_fini(struct lb_header *header);
 
-/* Routines to extract part so the linuxBIOS table or information
- * from the linuxBIOS table.
+/* Routines to extract part so the coreboot table or information
+ * from the coreboot table.
  */
 struct lb_memory *get_lb_mem(void);
 
 extern struct cmos_option_table option_table;
 
-#endif /* LINUXBIOS_TABLE_H */
+#endif /* COREBOOT_TABLE_H */
diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c
index 29fcc13da4..417d9a98bb 100644
--- a/src/arch/i386/boot/tables.c
+++ b/src/arch/i386/boot/tables.c
@@ -23,7 +23,7 @@ struct gdtarg {
 
 // Copy GDT to new location and reload it
 // 2003-07 by SONE Takeshi
-// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
+// Ported from Etherboot to coreboot 2005-08 by Steve Magnani
 void move_gdt(unsigned long newgdt)
 {
 	uint16_t num_gdt_bytes = &gdt_end - &gdt;
@@ -58,7 +58,7 @@ struct lb_memory *write_tables(void)
 
 	/* Write ACPI tables */
 	/* write them in the rom area because DSDT can be large (8K on epia-m) which
-	 * pushes linuxbios table out of first 4K if set up in low table area 
+	 * pushes coreboot table out of first 4K if set up in low table area 
 	 */
 	rom_table_end = write_acpi_tables(rom_table_end);
 	rom_table_end = (rom_table_end+1023) & ~1023;
@@ -105,8 +105,8 @@ struct lb_memory *write_tables(void)
 	move_gdt(low_table_end);
 	low_table_end += &gdt_end - &gdt;
 
-	/* The linuxbios table must be in 0-4K or 960K-1M */
-	write_linuxbios_table(low_table_start, low_table_end,
+	/* The coreboot table must be in 0-4K or 960K-1M */
+	write_coreboot_table(low_table_start, low_table_end,
 			      rom_table_start, rom_table_end);
 
 	return get_lb_mem();
diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h
index c8c26abaed..a69d8ca00f 100644
--- a/src/arch/i386/include/arch/acpi.h
+++ b/src/arch/i386/include/arch/acpi.h
@@ -1,5 +1,5 @@
 /*
- * Initial LinuxBIOS ACPI Support - headers and defines.
+ * coreboot ACPI Support - headers and defines.
  * 
  * written by Stefan Reinauer <stepan@openbios.org>
  * (C) 2004 SUSE LINUX AG
diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h
index 6cb6a767d9..0728193a9a 100644
--- a/src/arch/i386/include/arch/romcc_io.h
+++ b/src/arch/i386/include/arch/romcc_io.h
@@ -84,7 +84,7 @@ static inline int log2f(int value)
 
 typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
 
-/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G, 
+/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, 
  * We don't need to set %fs, and %gs anymore
  * Before that We need to use %gs, and leave %fs to other RAM access
  */
diff --git a/src/arch/i386/init/crt0.S.lb b/src/arch/i386/init/crt0.S.lb
index 952b8110cf..6a6c07be0e 100644
--- a/src/arch/i386/init/crt0.S.lb
+++ b/src/arch/i386/init/crt0.S.lb
@@ -16,7 +16,7 @@
  *
  * - Converted to gas assembly, and refitted to work with etherboot.
  *   Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of LinuxBIOS
+ * - Merged the nrv2b decompressor into crt0.base of coreboot
  *   Eric Biederman 26 Sept 2002
  */
 
@@ -65,7 +65,7 @@ __main:
 
 	cld				/* clear direction flag */
 	
-	/* copy linuxBIOS from it's initial load location to 
+	/* copy coreboot from it's initial load location to 
 	 * the location it is compiled to run at.
 	 * Normally this is copying from FLASH ROM to RAM.
 	 */
@@ -215,8 +215,8 @@ crt_console_tx_string:
 
 #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 .section ".rom.data"
-str_copying_to_ram:  .string "Copying LinuxBIOS to RAM.\r\n"
-str_pre_main:        .string "Jumping to LinuxBIOS.\r\n"
+str_copying_to_ram:  .string "Copying coreboot to RAM.\r\n"
+str_pre_main:        .string "Jumping to coreboot.\r\n"
 .previous
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
diff --git a/src/arch/i386/init/ldscript.lb b/src/arch/i386/init/ldscript.lb
index c902782681..578d121c84 100644
--- a/src/arch/i386/init/ldscript.lb
+++ b/src/arch/i386/init/ldscript.lb
@@ -7,7 +7,7 @@
  *				: heap
  *				: stack
  *	_ROMBASE
- *				: linuxbios text 
+ *				: coreboot text 
  *				: readonly text
  */
 /*
@@ -32,14 +32,14 @@ ENTRY(_start)
 */
 
 TARGET(binary)
-INPUT(linuxbios_ram.rom)
+INPUT(coreboot_ram.rom)
 SECTIONS
 {
 	. = _ROMBASE;
 
 	.ram . : {
 		_ram = . ;
-		linuxbios_ram.rom(*)
+		coreboot_ram.rom(*)
 		_eram = . ;
 	}
 
diff --git a/src/arch/i386/init/ldscript_apc.lb b/src/arch/i386/init/ldscript_apc.lb
index 43570ebe90..ce491547b0 100644
--- a/src/arch/i386/init/ldscript_apc.lb
+++ b/src/arch/i386/init/ldscript_apc.lb
@@ -1,9 +1,9 @@
-INPUT(linuxbios_apc.rom)
+INPUT(coreboot_apc.rom)
 SECTIONS
 {
         .apcrom . : {
                 _apcrom = .;
-                linuxbios_apc.rom(*)
+                coreboot_apc.rom(*)
                 _eapcrom = .;
         }
         _iseg_apc = DCACHE_RAM_BASE;
diff --git a/src/arch/i386/init/ldscript_failover.lb b/src/arch/i386/init/ldscript_failover.lb
index 12cb3feba8..207955b31a 100644
--- a/src/arch/i386/init/ldscript_failover.lb
+++ b/src/arch/i386/init/ldscript_failover.lb
@@ -7,7 +7,7 @@
  *				: heap
  *				: stack
  *	_ROMBASE
- *				: linuxbios text 
+ *				: coreboot text 
  *				: readonly text
  */
 /*
diff --git a/src/arch/i386/init/ldscript_fallback.lb b/src/arch/i386/init/ldscript_fallback.lb
index f2ffd1288c..be86fc2952 100644
--- a/src/arch/i386/init/ldscript_fallback.lb
+++ b/src/arch/i386/init/ldscript_fallback.lb
@@ -7,7 +7,7 @@
  *				: heap
  *				: stack
  *	_ROMBASE
- *				: linuxbios text 
+ *				: coreboot text 
  *				: readonly text
  */
 /*
@@ -32,14 +32,14 @@ ENTRY(_start)
 */
 
 TARGET(binary)
-INPUT(linuxbios_ram.rom)
+INPUT(coreboot_ram.rom)
 SECTIONS
 {
 	. = _ROMBASE;
 
 	.ram . : {
 		_ram = . ;
-		linuxbios_ram.rom(*)
+		coreboot_ram.rom(*)
 		_eram = . ;
 	}
 
diff --git a/src/arch/i386/lib/c_start.S b/src/arch/i386/lib/c_start.S
index 272209aca9..3145931e51 100644
--- a/src/arch/i386/lib/c_start.S
+++ b/src/arch/i386/lib/c_start.S
@@ -251,8 +251,8 @@ gdtaddr:
 
 	 .data
 
-	/* This is the gdt for GCC part of LinuxBIOS.
-	 * It is different from the gdt in ROMCC/ASM part of LinuxBIOS
+	/* This is the gdt for GCC part of coreboot.
+	 * It is different from the gdt in ROMCC/ASM part of coreboot
 	 * which is defined in entry32.inc */
 gdt:
 	/* selgdt 0, unused */
diff --git a/src/arch/i386/lib/console.c b/src/arch/i386/lib/console.c
index 993edb2a35..59bb1000be 100644
--- a/src/arch/i386/lib/console.c
+++ b/src/arch/i386/lib/console.c
@@ -19,19 +19,19 @@ static void __console_tx_byte(unsigned char byte)
 
 #endif /* CONFIG_USE_PRINTK_IN_CAR */
 
-#ifndef LINUXBIOS_EXTRA_VERSION
-#define LINUXBIOS_EXTRA_VERSION ""
+#ifndef COREBOOT_EXTRA_VERSION
+#define COREBOOT_EXTRA_VERSION ""
 #endif
 
 
 static void console_init(void)
 {
 	static const char console_test[] = 
-		"\r\n\r\nLinuxBIOS-"
-		LINUXBIOS_VERSION
-		LINUXBIOS_EXTRA_VERSION
+		"\r\n\r\ncoreboot-"
+		COREBOOT_VERSION
+		COREBOOT_EXTRA_VERSION
 		" "
-		LINUXBIOS_BUILD
+		COREBOOT_BUILD
 		" starting...\r\n";
 	print_info(console_test);
 }
diff --git a/src/arch/ppc/Config.lb b/src/arch/ppc/Config.lb
index 31ccc297ce..4e3c858c53 100644
--- a/src/arch/ppc/Config.lb
+++ b/src/arch/ppc/Config.lb
@@ -1,7 +1,7 @@
 ldscript init/ldscript.lb
 
-makerule linuxbios.rom 
-	depends	"linuxbios" 
+makerule coreboot.rom 
+	depends	"coreboot" 
 	action	"cp $< $@"
 end
 
diff --git a/src/arch/ppc/boot/boot.c b/src/arch/ppc/boot/boot.c
index 5a7d06d26e..b123b3e5f0 100644
--- a/src/arch/ppc/boot/boot.c
+++ b/src/arch/ppc/boot/boot.c
@@ -29,7 +29,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
 	 */
 	flush_dcache();
 
-	/* On ppc we don't currently support loading over LinuxBIOS.
+	/* On ppc we don't currently support loading over coreboot.
 	 * So ignore the buffer.
 	 */
 
diff --git a/src/arch/ppc/boot/linuxbios_table.c b/src/arch/ppc/boot/linuxbios_table.c
index e8eefc6258..2758934e2e 100644
--- a/src/arch/ppc/boot/linuxbios_table.c
+++ b/src/arch/ppc/boot/linuxbios_table.c
@@ -104,16 +104,16 @@ void lb_strings(struct lb_header *header)
 		uint32_t tag;
 		const uint8_t *string;
 	} strings[] = {
-		{ LB_TAG_VERSION,        linuxbios_version,        },
-		{ LB_TAG_EXTRA_VERSION,  linuxbios_extra_version,  },
-		{ LB_TAG_BUILD,          linuxbios_build,          },
-		{ LB_TAG_COMPILE_TIME,   linuxbios_compile_time,   },
-		{ LB_TAG_COMPILE_BY,     linuxbios_compile_by,     },
-		{ LB_TAG_COMPILE_HOST,   linuxbios_compile_host,   },
-		{ LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
-		{ LB_TAG_COMPILER,       linuxbios_compiler,       },
-		{ LB_TAG_LINKER,         linuxbios_linker,         },
-		{ LB_TAG_ASSEMBLER,      linuxbios_assembler,      },
+		{ LB_TAG_VERSION,        coreboot_version,        },
+		{ LB_TAG_EXTRA_VERSION,  coreboot_extra_version,  },
+		{ LB_TAG_BUILD,          coreboot_build,          },
+		{ LB_TAG_COMPILE_TIME,   coreboot_compile_time,   },
+		{ LB_TAG_COMPILE_BY,     coreboot_compile_by,     },
+		{ LB_TAG_COMPILE_HOST,   coreboot_compile_host,   },
+		{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
+		{ LB_TAG_COMPILER,       coreboot_compiler,       },
+		{ LB_TAG_LINKER,         coreboot_linker,         },
+		{ LB_TAG_ASSEMBLER,      coreboot_assembler,      },
 	};
 	unsigned int i;
 	for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
@@ -183,7 +183,7 @@ unsigned long lb_table_fini(struct lb_header *head)
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk_debug("Wrote linuxbios table at: %p - %p  checksum %lx\n",
+	printk_debug("Wrote coreboot table at: %p - %p  checksum %lx\n",
 		head, rec, head->table_checksum);
 	return (unsigned long)rec;
 }
@@ -297,8 +297,8 @@ static void lb_add_memory_range(struct lb_memory *mem,
 	lb_cleanup_memory_ranges(mem);
 }
 
-/* Routines to extract part so the linuxBIOS table or 
- * information from the linuxBIOS table after we have written it.
+/* Routines to extract part so the coreboot table or 
+ * information from the coreboot table after we have written it.
  * Currently get_lb_mem relies on a global we can change the
  * implementaiton.
  */
@@ -330,7 +330,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
 	return mem;
 }
 
-unsigned long write_linuxbios_table( 
+unsigned long write_coreboot_table( 
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end)
 {
@@ -363,9 +363,9 @@ unsigned long write_linuxbios_table(
 
 	/* Note:
 	 * I assume that there is always memory at immediately after
-	 * the low_table_end.  This means that after I setup the linuxbios table.
+	 * the low_table_end.  This means that after I setup the coreboot table.
 	 * I can trivially fixup the reserved memory ranges to hold the correct
-	 * size of the linuxbios table.
+	 * size of the coreboot table.
 	 */
 
 	/* Record our motheboard */
diff --git a/src/arch/ppc/boot/linuxbios_table.h b/src/arch/ppc/boot/linuxbios_table.h
index 25b152cd8c..2f200912f6 100644
--- a/src/arch/ppc/boot/linuxbios_table.h
+++ b/src/arch/ppc/boot/linuxbios_table.h
@@ -1,12 +1,12 @@
-#ifndef LINUXBIOS_TABLE_H
-#define LINUXBIOS_TABLE_H
+#ifndef COREBOOT_TABLE_H
+#define COREBOOT_TABLE_H
 
 #include <boot/linuxbios_tables.h>
 
 struct mem_range;
 
-/* This file holds function prototypes for building the linuxbios table. */
-unsigned long write_linuxbios_table(
+/* This file holds function prototypes for building the coreboot table. */
+unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end);
 
@@ -21,11 +21,11 @@ void lb_memory_range(struct lb_memory *mem,
 struct lb_mainboard *lb_mainboard(struct lb_header *header);
 unsigned long lb_table_fini(struct lb_header *header);
 
-/* Routines to extract part so the linuxBIOS table or information
- * from the linuxBIOS table.
+/* Routines to extract part so the coreboot table or information
+ * from the coreboot table.
  */
 struct lb_memory *get_lb_mem(void);
 
 extern struct cmos_option_table option_table;
 
-#endif /* LINUXBIOS_TABLE_H */
+#endif /* COREBOOT_TABLE_H */
diff --git a/src/arch/ppc/boot/tables.c b/src/arch/ppc/boot/tables.c
index 6fde37da24..a9e1e8eb0f 100644
--- a/src/arch/ppc/boot/tables.c
+++ b/src/arch/ppc/boot/tables.c
@@ -18,8 +18,8 @@ write_tables(void)
 	low_table_start = 0;
 	low_table_end = 16;
 
-	/* The linuxbios table must be in 0-4K or 960K-1M */
-	write_linuxbios_table(
+	/* The coreboot table must be in 0-4K or 960K-1M */
+	write_coreboot_table(
 		low_table_start, low_table_end,
 		rom_table_start, rom_table_end);
 
diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb
index 63a32b735d..4c48087237 100644
--- a/src/arch/ppc/init/ldscript.lb
+++ b/src/arch/ppc/init/ldscript.lb
@@ -5,7 +5,7 @@
  *	_RESET			: reset vector (may be at top of ROM)
  *	_EXCEPTIONS_VECTORS	: exception table
  *
- *	_ROMSTART 		: linuxbios text 
+ *	_ROMSTART 		: coreboot text 
  *				: payload text
  *
  *	_RAMBASE		: address to copy payload
@@ -26,7 +26,7 @@ OUTPUT_FORMAT("elf32-powerpc")
 ENTRY(_start)
 
 TARGET(binary)
-INPUT(linuxbios_ram.rom)
+INPUT(coreboot_ram.rom)
 SECTIONS
 {
 	/* 
@@ -54,7 +54,7 @@ SECTIONS
 	}
 
 	/*
-	 * Absolute location of LinuxBIOS initialization code in ROM.
+	 * Absolute location of coreboot initialization code in ROM.
 	 */
 	. = _ROMSTART;
 	.rom . : {
@@ -63,7 +63,7 @@ SECTIONS
 		*(.text);
 		*(.rom.data);
 		*(.rodata);
-		*(EXCLUDE_FILE(linuxbios_ram.rom) .data);
+		*(EXCLUDE_FILE(coreboot_ram.rom) .data);
 		. = ALIGN(16);
 		_erom = .;
 	}
@@ -71,16 +71,16 @@ SECTIONS
 	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
 	
 	/*
-	 * Ram is the LinuxBIOS code that runs from RAM.
+	 * Ram is the coreboot code that runs from RAM.
 	 */
 	.ram . : {
 		_ram = . ;
-		linuxbios_ram.rom(*)
+		coreboot_ram.rom(*)
 		_eram = . ;
 	}
 
 	/*
-	 * Absolute location of where LinuxBIOS will be relocated in RAM.
+	 * Absolute location of where coreboot will be relocated in RAM.
 	 */
 	_iseg = _RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
diff --git a/src/boot/elfboot.c b/src/boot/elfboot.c
index 6f307edd73..cb8e1cf28d 100644
--- a/src/boot/elfboot.c
+++ b/src/boot/elfboot.c
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-/* Maximum physical address we can use for the linuxBIOS bounce buffer.
+/* Maximum physical address we can use for the coreboot bounce buffer.
  */
 #ifndef MAX_ADDR
 #define MAX_ADDR -1UL
@@ -88,16 +88,16 @@ int verify_ip_checksum(
  * a machine, and implementing general relocation is hard.
  *
  * The solution:
- * - Allocate a buffer twice the size of the linuxBIOS image.
- * - Anything that would overwrite linuxBIOS copy into the lower half of
+ * - Allocate a buffer twice the size of the coreboot image.
+ * - Anything that would overwrite coreboot copy into the lower half of
  *   the buffer. 
- * - After loading an ELF image copy linuxBIOS to the upper half of the
+ * - After loading an ELF image copy coreboot to the upper half of the
  *   buffer.
  * - Then jump to the loaded image.
  * 
  * Benefits:
  * - Nearly arbitrary standalone executables can be loaded.
- * - LinuxBIOS is preserved, so it can be returned to.
+ * - Coreboot is preserved, so it can be returned to.
  * - The implementation is still relatively simple,
  *   and much simpler then the general case implemented in kexec.
  * 
@@ -110,7 +110,7 @@ static unsigned long get_bounce_buffer(struct lb_memory *mem)
 	unsigned long buffer;
 	int i;
 	lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
-	/* Double linuxBIOS size so I have somewhere to place a copy to return to */
+	/* Double coreboot size so I have somewhere to place a copy to return to */
 	lb_size = lb_size + lb_size;
 	mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
 	buffer = 0;
@@ -251,7 +251,7 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer,
 
 static void relocate_segment(unsigned long buffer, struct segment *seg)
 {
-	/* Modify all segments that want to load onto linuxBIOS
+	/* Modify all segments that want to load onto coreboot
 	 * to load onto the bounce buffer instead.
 	 */
 	unsigned long lb_start = (unsigned long)&_ram_seg;
@@ -264,7 +264,7 @@ static void relocate_segment(unsigned long buffer, struct segment *seg)
 	start = seg->s_addr;
 	middle = start + seg->s_filesz;
 	end = start + seg->s_memsz;
-	/* I don't conflict with linuxBIOS so get out of here */
+	/* I don't conflict with coreboot so get out of here */
 	if ((end <= lb_start) || (start >= lb_end))
 		return;
 
@@ -272,7 +272,7 @@ static void relocate_segment(unsigned long buffer, struct segment *seg)
 		start, middle, end);
 
 	/* Slice off a piece at the beginning
-	 * that doesn't conflict with linuxBIOS.
+	 * that doesn't conflict with coreboot.
 	 */
 	if (start < lb_start) {
 		struct segment *new;
@@ -311,7 +311,7 @@ static void relocate_segment(unsigned long buffer, struct segment *seg)
 	}
 	
 	/* Slice off a piece at the end 
-	 * that doesn't conflict with linuxBIOS 
+	 * that doesn't conflict with coreboot 
 	 */
 	if (end > lb_end) {
 		unsigned long len = lb_end - start;
@@ -545,7 +545,7 @@ int elfload(struct lb_memory *mem,
 	struct verify_callback *cb_chain;
 	unsigned long bounce_buffer;
 
-	/* Find a bounce buffer so I can load to linuxBIOS's current location */
+	/* Find a bounce buffer so I can load to coreboot's current location */
 	bounce_buffer = get_bounce_buffer(mem);
 	if (!bounce_buffer) {
 		printk_err("Could not find a bounce buffer...\n");
diff --git a/src/boot/filo.c b/src/boot/filo.c
index f5c5bda420..157bec2057 100644
--- a/src/boot/filo.c
+++ b/src/boot/filo.c
@@ -2,7 +2,7 @@
  * Copyright (C) 2003 by SONE Takeshi <ts1@tsn.or.jp> and others.
  * This program is licensed under the terms of GNU General Public License.
  *
- * Modified for LinuxBIOS by Greg Watson <gwatson@lanl.gov>
+ * Modified for coreboot by Greg Watson <gwatson@lanl.gov>
  */
 
 #include <console/console.h>
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index eb971246c2..cc3741f583 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -22,7 +22,7 @@ it with the version available from LANL.
 
 
 /*
- * C Bootstrap code for the LinuxBIOS
+ * C Bootstrap code for the coreboot
  */
 
 
@@ -38,9 +38,9 @@ it with the version available from LANL.
 #include <boot/elf.h>
 
 /**
- * @brief Main function of the DRAM part of LinuxBIOS.
+ * @brief Main function of the DRAM part of coreboot.
  *
- * LinuxBIOS is divided into Pre-DRAM part and DRAM part. 
+ * Coreboot is divided into Pre-DRAM part and DRAM part. 
  *
  * 
  * Device Enumeration:
@@ -57,8 +57,8 @@ void hardwaremain(int boot_complete)
 	
 	post_code(0x39);
 
-	printk_notice("LinuxBIOS-%s%s %s %s...\n", 
-		      linuxbios_version, linuxbios_extra_version, linuxbios_build,
+	printk_notice("coreboot-%s%s %s %s...\n", 
+		      coreboot_version, coreboot_extra_version, coreboot_build,
 		      (boot_complete)?"rebooting":"booting");
 
 	post_code(0x40);
diff --git a/src/config/Config.lb b/src/config/Config.lb
index 37852e1d15..76b44b7c65 100644
--- a/src/config/Config.lb
+++ b/src/config/Config.lb
@@ -27,102 +27,102 @@ end
 #	action	"perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@"
 #end
 
-makerule linuxbios.strip  
-	depends	"linuxbios" 
-	action	"$(OBJCOPY) -O binary linuxbios linuxbios.strip"
+makerule coreboot.strip  
+	depends	"coreboot" 
+	action	"$(OBJCOPY) -O binary coreboot coreboot.strip"
 end
 
-makerule linuxbios.a
+makerule coreboot.a
         depends "$(OBJECTS)"
-        action  "rm -f linuxbios.a"
-        action  "ar cr linuxbios.a $(OBJECTS)"
+        action  "rm -f coreboot.a"
+        action  "ar cr coreboot.a $(OBJECTS)"
 end
 
-makerule linuxbios_ram.o
-	depends	"$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)" 
-	action	"$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)"
+makerule coreboot_ram.o
+	depends	"$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
+	action	"$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)"
 end
 
-makerule linuxbios_ram
-	depends	"linuxbios_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions" 
-	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld linuxbios_ram.o"
-	action 	"$(CROSS_COMPILE)nm -n linuxbios_ram | sort > linuxbios_ram.map"
+makerule coreboot_ram
+	depends	"coreboot_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions" 
+	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld coreboot_ram.o"
+	action 	"$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
 end
 
 ##
-## By default compress the part of linuxbios that runs from RAM
+## By default compress the part of coreboot that runs from RAM
 ##
-makedefine LINUXBIOS_RAM-$(CONFIG_COMPRESS):=linuxbios_ram.nrv2b
-makedefine LINUXBIOS_RAM-$(CONFIG_UNCOMPRESSED):=linuxbios_ram.bin
+makedefine COREBOOT_RAM-$(CONFIG_COMPRESS):=coreboot_ram.nrv2b
+makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
 
-makerule linuxbios_ram.bin 
-	depends	"linuxbios_ram" 
+makerule coreboot_ram.bin 
+	depends	"coreboot_ram" 
 	action	"$(OBJCOPY) -O binary $< $@"
 end
 
-makerule linuxbios_ram.nrv2b 
-	depends	"linuxbios_ram.bin nrv2b" 
+makerule coreboot_ram.nrv2b 
+	depends	"coreboot_ram.bin nrv2b" 
 	action	"./nrv2b e $< $@"
 end
 
-makerule linuxbios_ram.rom
-	depends	"$(LINUXBIOS_RAM-1)" 
-	action	"cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
+makerule coreboot_ram.rom
+	depends	"$(COREBOOT_RAM-1)" 
+	action	"cp $(COREBOOT_RAM-1) coreboot_ram.rom"
 end
 
-makedefine LINUXBIOS_APC:=
+makedefine COREBOOT_APC:=
 
 if CONFIG_AP_CODE_IN_CAR
 	#for ap code in cache
 
-	makerule linuxbios_apc.a
+	makerule coreboot_apc.a
 		depends "apc_auto.o"
-		action  "rm -f linuxbios_apc.a"
-		action  "ar cr linuxbios_apc.a apc_auto.o"
+		action  "rm -f coreboot_apc.a"
+		action  "ar cr coreboot_apc.a apc_auto.o"
 	end
 
-	makerule linuxbios_apc.o
-		depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)"
-        action  "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)"
+	makerule coreboot_apc.o
+		depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)"
+        action  "$(CC) -nostdlib -r -o $@ c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
 	end
 
-	makerule linuxbios_apc
-		depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
-		action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o"
-		action  "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map"
+	makerule coreboot_apc
+		depends "coreboot_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions"
+		action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld coreboot_apc.o"
+		action  "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
 	end
 
 	##
-	## By default compress the part of linuxbios that runs from cache as ram
+	## By default compress the part of coreboot that runs from cache as ram
 	##
-	makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b
-	makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin
+	makedefine COREBOOT_APC-$(CONFIG_COMPRESS):=coreboot_apc.nrv2b
+	makedefine COREBOOT_APC-$(CONFIG_UNCOMPRESSED):=coreboot_apc.bin
 
-	makerule linuxbios_apc.bin
-		depends "linuxbios_apc"
+	makerule coreboot_apc.bin
+		depends "coreboot_apc"
 		action  "$(OBJCOPY) -O binary $< $@"
 	end
 
-	makerule linuxbios_apc.nrv2b
-        depends "linuxbios_apc.bin nrv2b"
+	makerule coreboot_apc.nrv2b
+        depends "coreboot_apc.bin nrv2b"
         action  "./nrv2b e $< $@"
 	end
 
-	makerule linuxbios_apc.rom
-		depends "$(LINUXBIOS_APC-1)"
-		action  "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom"
+	makerule coreboot_apc.rom
+		depends "$(COREBOOT_APC-1)"
+		action  "cp $(COREBOOT_APC-1) coreboot_apc.rom"
 	end
 
-	makedefine LINUXBIOS_APC:=linuxbios_apc.rom
+	makedefine COREBOOT_APC:=coreboot_apc.rom
 
 end
 
-makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom
+makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
 
-makerule linuxbios   
-	depends	"crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
+makerule coreboot   
+	depends	"crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
 	action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
-	action	"$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
+	action	"$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
 end
 
 #makerule crt0.S   
@@ -158,14 +158,14 @@ makerule tags
 	depends	"$(SOURCES)" 
 	action	"ctags $(SOURCES)"
 end
-makerule LinuxBIOSDoc.config
-	depends	"$(TOP)/src/config/LinuxBIOSDoc.config" 
-	action "cat $(TOP)/src/config/LinuxBIOSDoc.config > LinuxBIOSDoc.config"
-        action "echo 'INPUT=$(SOURCES)' >> LinuxBIOSDoc.config"
+makerule corebootDoc.config
+	depends	"$(TOP)/src/config/corebootDoc.config" 
+	action "cat $(TOP)/src/config/corebootDoc.config > corebootDoc.config"
+        action "echo 'INPUT=$(SOURCES)' >> corebootDoc.config"
 end
 makerule documentation   
-	depends	"LinuxBIOSDoc.config"
-	action	"doxygen LinuxBIOSDoc.config"
+	depends	"corebootDoc.config"
+	action	"doxygen corebootDoc.config"
 end
 
 makerule ./romcc   
@@ -204,12 +204,12 @@ object ./option_table.o
 end
 
 makerule clean  
-	action	"rm -f linuxbios.* *~"
-	action	"rm -f linuxbios"
+	action	"rm -f coreboot.* *~"
+	action	"rm -f coreboot"
 	action	"rm -f ldscript.ld"
 	action	"rm -f a.out *.s *.l *.o *.E *.inc"
 	action	"rm -f TAGS tags romcc*"
-	action	"rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*"
+	action	"rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
 	action	"rm -f build_opt_tbl* nrv2b* option_table.c crt0.S"
 end
 
diff --git a/src/config/LinuxBIOSDoc.config b/src/config/LinuxBIOSDoc.config
index d8ef8b7bee..27d17caf11 100755
--- a/src/config/LinuxBIOSDoc.config
+++ b/src/config/LinuxBIOSDoc.config
@@ -3,7 +3,7 @@
 #---------------------------------------------------------------------------
 # Project related configuration options
 #---------------------------------------------------------------------------
-PROJECT_NAME           = LinuxBIOS
+PROJECT_NAME           = coreboot
 PROJECT_NUMBER         = 
 OUTPUT_DIRECTORY       = .
 CREATE_SUBDIRS         = NO
diff --git a/src/config/Options.lb b/src/config/Options.lb
index e6ec087a64..7b22ea8692 100644
--- a/src/config/Options.lb
+++ b/src/config/Options.lb
@@ -1,6 +1,6 @@
 #######################################################
 #
-# Main options file for LinuxBIOS
+# Main options file for coreboot
 #
 # Each option used by a part must be defined in
 # this file. The format for options is:
@@ -96,62 +96,62 @@ define OBJCOPY
 	export always
 	comment "Objcopy command"
 end
-define LINUXBIOS_VERSION
+define COREBOOT_VERSION
 	default "2.0.0"
 	export always
 	format "\"%s\""
-	comment "LinuxBIOS version"
+	comment "coreboot version"
 end
-define LINUXBIOS_EXTRA_VERSION
+define COREBOOT_EXTRA_VERSION
         default ""
         export used
 	format "\"%s\""
-        comment "LinuxBIOS extra version"
+        comment "coreboot extra version"
 end
-define LINUXBIOS_BUILD
+define COREBOOT_BUILD
 	default "$(shell date)"
 	export always
 	format "\"%s\""
 	comment "Build date"
 end
-define LINUXBIOS_COMPILE_TIME
+define COREBOOT_COMPILE_TIME
 	default "$(shell date +%T)"
 	export always
 	format "\"%s\""
 	comment "Build time"
 end
-define LINUXBIOS_COMPILE_BY
+define COREBOOT_COMPILE_BY
 	default "$(shell whoami)"
 	export always
 	format "\"%s\""
 	comment "Who build this image"
 end
-define LINUXBIOS_COMPILE_HOST
+define COREBOOT_COMPILE_HOST
 	default "$(shell hostname)"
 	export always
 	format "\"%s\""
 	comment "Build host"
 end
 
-define LINUXBIOS_COMPILE_DOMAIN
+define COREBOOT_COMPILE_DOMAIN
 	default "$(shell dnsdomainname)"
 	export always
 	format "\"%s\""
 	comment "Build domain name"
 end
-define LINUXBIOS_COMPILER
+define COREBOOT_COMPILER
 	default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
 	export always
 	format "\"%s\""
 	comment "Build compiler"
 end
-define LINUXBIOS_LINKER
+define COREBOOT_LINKER
 	default "$(shell  $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
 	export always
 	format "\"%s\""
 	comment "Build linker"
 end
-define LINUXBIOS_ASSEMBLER
+define COREBOOT_ASSEMBLER
 	default "$(shell  touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
 	export always
 	format "\"%s\""
@@ -242,13 +242,13 @@ define _ROMBASE
 	default {PAYLOAD_SIZE}
 	format "0x%x"
 	export always
-	comment "Base address of LinuxBIOS in ROM"
+	comment "Base address of coreboot in ROM"
 end
 define _ROMSTART
 	default none
 	format "0x%x"
 	export used
-	comment "Start address of LinuxBIOS in ROM"
+	comment "Start address of coreboot in ROM"
 end
 define _RESET
 	default {_ROMBASE}
@@ -278,13 +278,13 @@ define _RAMBASE
 	default none
 	format "0x%x"
 	export always
-	comment "Base address of LinuxBIOS in RAM"
+	comment "Base address of coreboot in RAM"
 end
 define _RAMSTART
 	default none
 	format "0x%x"
 	export used
-	comment "Start address of LinuxBIOS in RAM"
+	comment "Start address of coreboot in RAM"
 end
 define USE_DCACHE_RAM
 	default 0
@@ -317,7 +317,7 @@ end
 define CONFIG_AP_CODE_IN_CAR
         default 0
         export always
-        comment "will copy linuxbios_apc to AP cache ane execute in AP"
+        comment "will copy coreboot_apc to AP cache ane execute in AP"
 end
 define MEM_TRAIN_SEQ
         default 0
@@ -333,13 +333,13 @@ define XIP_ROM_BASE
 	default 0
 	format "0x%x"
 	export used
-	comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
+	comment "Start address of area to cache during coreboot execution directly from ROM"
 end
 define XIP_ROM_SIZE
 	default 0
 	format "0x%x"
 	export used
-	comment "Size of area to cache during LinuxBIOS execution directly from ROM"
+	comment "Size of area to cache during coreboot execution directly from ROM"
 end
 define CONFIG_COMPRESS
 	default 1
@@ -377,13 +377,13 @@ define LB_CKS_RANGE_START
 	default 49
 	format "%d"
 	export always
-	comment "First CMOS byte to use for LinuxBIOS options"
+	comment "First CMOS byte to use for coreboot options"
 end
 define LB_CKS_RANGE_END
 	default 125
 	format "%d"
 	export always
-	comment "Last CMOS byte to use for LinuxBIOS options"
+	comment "Last CMOS byte to use for coreboot options"
 end
 define LB_CKS_LOC
 	default 126
diff --git a/src/config/doxyscript.base b/src/config/doxyscript.base
index 557b952ee5..0a14e908d1 100755
--- a/src/config/doxyscript.base
+++ b/src/config/doxyscript.base
@@ -16,7 +16,7 @@
 # The PROJECT_NAME tag is a single word (or a sequence of words surrounded 
 # by quotes) that should identify the project. 
 
-PROJECT_NAME           = "LinuxBIOS"
+PROJECT_NAME           = "coreboot"
 
 # The PROJECT_NUMBER tag can be used to enter a project or revision number. 
 # This could be handy for archiving the generated documentation or 
diff --git a/src/config/linuxbios_apc.ld b/src/config/linuxbios_apc.ld
index 9bf1dac7e8..9bca028ca1 100644
--- a/src/config/linuxbios_apc.ld
+++ b/src/config/linuxbios_apc.ld
@@ -15,7 +15,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+ *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
  *  2006.05 yhlu tailed it to use it for AP code in cache
  */
 /*
@@ -85,12 +85,12 @@ SECTIONS
         }
         _eheap = .;
 	/* The ram segment
- 	 * This is all address of the memory resident copy of linuxBIOS.
+ 	 * This is all address of the memory resident copy of coreboot.
 	 */
 	_ram_seg = _text; 
 	_eram_seg = _eheap;
 
-	_bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "linuxbios_apc is too big");
+	_bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
 
 	/DISCARD/ : {
 		*(.comment)
diff --git a/src/config/linuxbios_ram.ld b/src/config/linuxbios_ram.ld
index fb68373f1b..5af6e74100 100644
--- a/src/config/linuxbios_ram.ld
+++ b/src/config/linuxbios_ram.ld
@@ -15,7 +15,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+ *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
  */
 /*
  *	We use ELF as output format. So that we can
@@ -57,7 +57,7 @@ SECTIONS
 		/*
 		 * kevinh/Ispiri - Added an align, because the objcopy tool
 		 * incorrectly converts sections that are not long word aligned.
-		 * This breaksthe linuxbios.strip target.
+		 * This breaks the coreboot.strip target.
 		 */
 		 . = ALIGN(4);
 
@@ -104,7 +104,7 @@ SECTIONS
         }
         _eheap = .;
 	/* The ram segment
- 	 * This is all address of the memory resident copy of linuxBIOS.
+ 	 * This is all address of the memory resident copy of coreboot.
 	 */
 	_ram_seg = _text; 
 	_eram_seg = _eheap;
diff --git a/src/console/btext_console.c b/src/console/btext_console.c
index bf2c555881..b1b10e63cb 100644
--- a/src/console/btext_console.c
+++ b/src/console/btext_console.c
@@ -3,7 +3,7 @@
  *
  * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  *
- *   move to LinuxBIOS by LYH yhlu@tyan.com
+ *   move to coreboot by LYH yhlu@tyan.com
  */
 
 #if 0
diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c
index a97ad309b1..e692853385 100644
--- a/src/cpu/amd/car/copy_and_run.c
+++ b/src/cpu/amd/car/copy_and_run.c
@@ -23,7 +23,7 @@ static void copy_and_run(void)
 	uint8_t *src, *dst; 
         unsigned long ilen, olen;
 
-	print_debug("Copying LinuxBIOS to RAM.\r\n");
+	print_debug("Copying coreboot to RAM.\r\n");
 
 #if !CONFIG_COMPRESS 
 	__asm__ volatile (
@@ -55,7 +55,7 @@ static void copy_and_run(void)
 
 	print_debug_cp_run("linxbios_ram.bin   length = ", olen);
 
-	print_debug("Jumping to LinuxBIOS.\r\n");
+	print_debug("Jumping to coreboot.\r\n");
 
         __asm__ volatile (
                 "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
@@ -73,7 +73,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
         uint8_t *src, *dst;
         unsigned long ilen, olen;
 
-//        print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
+//        print_debug("Copying coreboot AP code to CAR.\r\n");
 
 #if !CONFIG_COMPRESS
         __asm__ volatile (
@@ -105,7 +105,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
 
 //        print_debug_cp_run("linxbios_apc.bin   length = ", olen);
 
-//        print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
+//        print_debug("Jumping to coreboot AP code in CAR.\r\n");
 
         __asm__ volatile (
                 "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index fc30ee9ab1..0f5f831270 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -21,7 +21,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
         "wrmsr\n\t"
 #endif
 
-        /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
+        /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
         "movl    $0xC0010010, %ecx\n\t"
 //        "movl    $SYSCFG_MSR, %ecx\n\t"
         "rdmsr\n\t"
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 7074f23c5a..ce8ef19647 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -104,7 +104,7 @@ static void post_cache_as_ram(void)
         // wait for ap memory to trained
 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
 #endif
-        /*copy and execute linuxbios_ram */
+        /*copy and execute coreboot_ram */
         copy_and_run();
         /* We will not return */
 
diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index add010b790..8c0adf891a 100644
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -10,7 +10,7 @@
 /* what a mess this uncompress thing is. I am not at all happy about how this 
  * was done, but can't fix it yet. RGM
  */
-#warning "Fix the uncompress once linuxbios knows how to do it"
+#warning "Fix the uncompress once coreboot knows how to do it"
 #include "../lib/nrv2b.c"
 
 /* vsmsetup.c derived from vgabios.c. Derived from: */
@@ -71,7 +71,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used 
-   without reliance on other parts of core Linuxbios 
+   without reliance on other parts of core coreboot 
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -320,10 +320,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords, 
 // and pop to protected mode. 
-// second, since this only ever runs as part of linuxbios, 
+// second, since this only ever runs as part of coreboot, 
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to 
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index acd85c5185..a92f474457 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
 #define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
 
 #define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
@@ -213,7 +213,7 @@ __main:
 
 	cld				/* clear direction flag */
 
-	/* copy linuxBIOS from it's initial load location to
+	/* copy coreboot from it's initial load location to
 	 * the location it is compiled to run at.
 	 * Normally this is copying from FLASH ROM to RAM.
 	 */
@@ -363,8 +363,8 @@ crt_console_tx_string:
 
 #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 .section ".rom.data"
-str_copying_to_ram:  .string "Copying LinuxBIOS to ram.\r\n"
-str_pre_main:        .string "Jumping to LinuxBIOS.\r\n"
+str_copying_to_ram:  .string "Copying coreboot to ram.\r\n"
+str_pre_main:        .string "Jumping to coreboot.\r\n"
 .previous
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index ec0b047907..baf96c0bbc 100644
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -75,7 +75,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used
-   without reliance on other parts of core Linuxbios
+   without reliance on other parts of core coreboot
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -341,10 +341,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords,
 // and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 95a2cd7414..2ec3f5a47e 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -157,7 +157,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* these are ENDING addresses, not sizes. 
 			 * if there is memory in this slot, then reg will be > rambits.
 			 * So we just take the max, that gives us total. 
-			 * We take the highest one to cover for once and future linuxbios
+			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
diff --git a/src/cpu/emulation/qemu-i386/northbridge.c b/src/cpu/emulation/qemu-i386/northbridge.c
index 07c8a9b4aa..505511ac95 100644
--- a/src/cpu/emulation/qemu-i386/northbridge.c
+++ b/src/cpu/emulation/qemu-i386/northbridge.c
@@ -86,7 +86,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* these are ENDING addresses, not sizes. 
 			 * if there is memory in this slot, then reg will be > rambits.
 			 * So we just take the max, that gives us total. 
-			 * We take the highest one to cover for once and future linuxbios
+			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb
index 8665fa35c0..ee65e41f3b 100644
--- a/src/cpu/ppc/mpc74xx/Config.lb
+++ b/src/cpu/ppc/mpc74xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
 ## Use cache ram for initial setup
 ##
 default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
 default DCACHE_RAM_BASE=_RAMBASE+0x100000
 ## Dcache size is 32Kb
 default DCACHE_RAM_SIZE=0x8000
diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index aa55df8789..ba2c0018d5 100644
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -19,7 +19,7 @@
 
 /*
  * The aim of this code is to bring the machine from power-on to the point 
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
  * which is written in C.
  *
  * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@@ -79,7 +79,7 @@
 	isync
 
 	/*
-	 * Clear segment registers (LinuxBIOS doesn't use these)
+	 * Clear segment registers (coreboot doesn't use these)
 	 */
 	mtsr    0, r0
 	isync
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb
index 4bf4638762..f739495325 100644
--- a/src/cpu/ppc/ppc4xx/Config.lb
+++ b/src/cpu/ppc/ppc4xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
 ## PPC4XX always uses cache ram for initial setup
 ##
 default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
 default DCACHE_RAM_BASE=_RAMBASE+0x100000
 ## Dcache size is 16Kb
 default DCACHE_RAM_SIZE=16384
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb
index dc2c025511..d6e64b379b 100644
--- a/src/cpu/ppc/ppc7xx/Config.lb
+++ b/src/cpu/ppc/ppc7xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
 ## PPC7XX always uses cache ram for initial setup
 ##
 default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
 default DCACHE_RAM_BASE=_RAMBASE+0x100000
 ## Dcache size is 16Kb
 default DCACHE_RAM_SIZE=16384
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
index 11b54c4207..bd599f324e 100644
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc
@@ -19,7 +19,7 @@
 
 /*
  * The aim of this code is to bring the machine from power-on to the point 
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
  * which is written in C.
  *
  * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@@ -72,7 +72,7 @@
 	isync
 
 	/*
-	 * Clear segment registers (LinuxBIOS doesn't use these)
+	 * Clear segment registers (coreboot doesn't use these)
 	 */
 	li	r3, 15
 1:	mtsrin  r3, r0
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 1c18a502fa..2cea40f8a7 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -1,4 +1,4 @@
-/* For starting linuxBIOS in protected mode */
+/* For starting coreboot in protected mode */
 
 #include <arch/rom_segs.h>
 
@@ -8,8 +8,8 @@
 	.align	4
 .globl gdtptr
 
-	/* This is the gdt for ROMCC/ASM part of LinuxBIOS.
-	 * It is different from the gdt in GCC part of LinuxBIOS
+	/* This is the gdt for ROMCC/ASM part of coreboot.
+	 * It is different from the gdt in GCC part of coreboot
 	 * which is defined in c_start.S */
 gdt:
 gdtptr:
diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c
index 6baf53ec8f..a7ccf9c173 100644
--- a/src/cpu/x86/car/copy_and_run.c
+++ b/src/cpu/x86/car/copy_and_run.c
@@ -15,7 +15,7 @@ static void copy_and_run(unsigned cpu_reset)
 	unsigned long dst_len;
         unsigned long ilen, olen;
 
-	print_debug("Copying LinuxBIOS to RAM.\r\n");
+	print_debug("Copying coreboot to RAM.\r\n");
 
 #if !CONFIG_COMPRESS 
 	__asm__ volatile (
@@ -53,7 +53,7 @@ static void copy_and_run(unsigned cpu_reset)
 #else
 	print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
 #endif
-	print_debug("Jumping to LinuxBIOS.\r\n");
+	print_debug("Jumping to coreboot.\r\n");
 
 	if(cpu_reset == 1 ) {
 		__asm__ volatile (
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 1adafc8d18..0bc8bbaf07 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -1,5 +1,5 @@
 /*
-	2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
 	2005.12 yhlu add _RAMBASE above 1M support for SMP
 */
 
@@ -191,7 +191,7 @@ static int lapic_start_cpu(unsigned long apicid)
 	return 1;
 }
 
-/* Number of cpus that are currently running in linuxbios */
+/* Number of cpus that are currently running in coreboot */
 static atomic_t active_cpus = ATOMIC_INIT(1);
 
 /* start_cpu_lock covers last_cpu_index and secondary_stack.
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 53db758ce2..2ccee666d8 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -1,5 +1,5 @@
 /*
-	2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
 */
 
 #include <console/console.h>
diff --git a/src/devices/emulator/x86emu/sys.c b/src/devices/emulator/x86emu/sys.c
index 62e1a53259..6ff268674a 100644
--- a/src/devices/emulator/x86emu/sys.c
+++ b/src/devices/emulator/x86emu/sys.c
@@ -45,7 +45,7 @@
 #include <x86emu/regs.h>
 #include "debug.h"
 #include "prim_ops.h"
-#ifdef LINUXBIOS_VERSION
+#ifdef COREBOOT_VERSION
 #include "arch/io.h"
 #else
 #include <sys/io.h>
diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index aedd7c02d4..4a0f8b38e3 100644
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -7,7 +7,7 @@
  *         	stevel@mvista.com or source@mvista.com
  *  Copyright (C) 2004 Tyan Computer.
  *  Auther: Yinghai Lu   yhlu@tyan.com
- *	   move to LinuxBIOS
+ *	   move to coreboot
  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  */
 #include <delay.h>
diff --git a/src/drivers/pci/onboard/onboard.c b/src/drivers/pci/onboard/onboard.c
index 6da5a0782e..51550803dd 100644
--- a/src/drivers/pci/onboard/onboard.c
+++ b/src/drivers/pci/onboard/onboard.c
@@ -24,8 +24,8 @@
 	in your MB targets Config.lb, afer romimage "normal"
 	3. create you vgabios.bin under normal bios and put that in dir that targets Config residues.
 		# dd if=/dev/mem of=atix.rom skip=1536 count=96
-	4. after build linuxbios.rom
-		# cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > linuxbios.rom
+	4. after build coreboot.rom
+		# cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
 	or use nsxv to build you image
 		# time ./nsxv s2850
 
@@ -52,8 +52,8 @@ eval make &> "$LBROOT/x_m.txt"
                 tail -n 15 "$LBROOT/x_m.txt"
                 exit
         fi
-cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > "$LBROOT/rom/"$MBMODEL"_linuxbios.rom"
-cp -f "$LBROOT/rom/"$MBMODEL"_linuxbios.rom" /home/yhlu/
+cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
+cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
 
 date
 
diff --git a/src/include/boot/elf.h b/src/include/boot/elf.h
index 3503388078..36ad670d4c 100644
--- a/src/include/boot/elf.h
+++ b/src/include/boot/elf.h
@@ -394,7 +394,7 @@ extern void jmp_to_elf_entry(void *entry, unsigned long buffer);
 struct lb_memory;
 extern int elfboot(struct lb_memory *mem);
 
-#define FIRMWARE_TYPE "LinuxBIOS"
+#define FIRMWARE_TYPE "coreboot"
 #define BOOTLOADER "elfboot"
 #define BOOTLOADER_VERSION "1.3"
 
diff --git a/src/include/boot/linuxbios_tables.h b/src/include/boot/linuxbios_tables.h
index 527c44d5fc..84bd99f515 100644
--- a/src/include/boot/linuxbios_tables.h
+++ b/src/include/boot/linuxbios_tables.h
@@ -1,9 +1,9 @@
-#ifndef LINUXBIOS_TABLES_H
-#define LINUXBIOS_TABLES_H
+#ifndef COREBOOT_TABLES_H
+#define COREBOOT_TABLES_H
 
 #include <stdint.h>
 
-/* The linuxbios table information is for conveying information
+/* The coreboot table information is for conveying information
  * from the firmware to the loaded OS image.  Primarily this
  * is expected to be information that cannot be discovered by
  * other means, such as quering the hardware directly.
@@ -31,12 +31,12 @@
  * table entries and be backwards compatible, but it is not required.
  */
 
-/* Since LinuxBIOS is usually compiled 32bit, gcc will align 64bit 
- * types to 32bit boundaries. If the LinuxBIOS table is dumped on a 
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit 
+ * types to 32bit boundaries. If the coreboot table is dumped on a 
  * 64bit system, a uint64_t would be aligned to 64bit boundaries, 
  * breaking the table format.
  *
- * lb_uint64 will keep 64bit LinuxBIOS table values aligned to 32bit
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
  * to ensure compatibility. They can be accessed with the two functions
  * below: unpack_lb64() and pack_lb64()
  *
@@ -213,4 +213,4 @@ struct	cmos_checksum {
 
 
 
-#endif /* LINUXBIOS_TABLES_H */
+#endif /* COREBOOT_TABLES_H */
diff --git a/src/include/console/btext.h b/src/include/console/btext.h
index d184a4bf35..88d93931b9 100644
--- a/src/include/console/btext.h
+++ b/src/include/console/btext.h
@@ -4,7 +4,7 @@
  *
  * Written by Benjamin Herrenschmidt.
  *  
- * Move to LinuxBIOS by LYH  yhlu@tyan.com
+ * Move to coreboot by LYH  yhlu@tyan.com
  *
  */
 
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 3eb79db129..0070c97dae 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2507,7 +2507,7 @@
 #define PCI_DEVICE_ID_SIS_SIS968_PCIE	0x000a  /* D6F0,D7F0 */
 #define PCI_DEVICE_ID_SIS_SIS968_HD_AUDIO	0x7502	/* DfF0 */
 
-/* OLD USAGE FOR LINUXBIOS */
+/* OLD USAGE FOR COREBOOT */
 #define PCI_VENDOR_ID_ACER              0x10b9
 #define PCI_DEVICE_ID_ACER_M1535D         0x1533
 
diff --git a/src/include/version.h b/src/include/version.h
index 223b9a3f75..af838b68ad 100644
--- a/src/include/version.h
+++ b/src/include/version.h
@@ -5,18 +5,18 @@
 extern const char mainboard_vendor[];
 extern const char mainboard_part_number[];
 
-/* LinuxBIOS Version */
-extern const char linuxbios_version[];
-extern const char linuxbios_extra_version[];
-extern const char linuxbios_build[];
+/* coreboot Version */
+extern const char coreboot_version[];
+extern const char coreboot_extra_version[];
+extern const char coreboot_build[];
 
-/* When LinuxBIOS was compiled */
-extern const char linuxbios_compile_time[];
-extern const char linuxbios_compile_by[];
-extern const char linuxbios_compile_host[];
-extern const char linuxbios_compile_domain[];
-extern const char linuxbios_compiler[];
-extern const char linuxbios_linker[];
-extern const char linuxbios_assembler[];
+/* When coreboot was compiled */
+extern const char coreboot_compile_time[];
+extern const char coreboot_compile_by[];
+extern const char coreboot_compile_host[];
+extern const char coreboot_compile_domain[];
+extern const char coreboot_compiler[];
+extern const char coreboot_linker[];
+extern const char coreboot_assembler[];
 
 #endif /* VERSION_H */
diff --git a/src/include/x86emu/x86emu.h b/src/include/x86emu/x86emu.h
index 9f29c4ccbe..bd45fea423 100644
--- a/src/include/x86emu/x86emu.h
+++ b/src/include/x86emu/x86emu.h
@@ -43,7 +43,7 @@
 #define __X86EMU_X86EMU_H
 
 /* FIXME: undefine printk for the moment */
-#ifdef LINUXBIOS_VERSION
+#ifdef COREBOOT_VERSION
 #include "console/console.h"
 #define printk printk_debug
 #else
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index 42746e1029..8e4ed3964f 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -1,6 +1,6 @@
 /* 
 
-LinuxBIOS interface to memory-saving variant of LZMA decoder
+Coreboot interface to memory-saving variant of LZMA decoder
 (C)opyright 2006 Carl-Daniel Hailfinger
 Released under the GNU GPL
 
diff --git a/src/lib/usbdebug_direct.c b/src/lib/usbdebug_direct.c
index 4b9affea93..50097f3e4c 100644
--- a/src/lib/usbdebug_direct.c
+++ b/src/lib/usbdebug_direct.c
@@ -5,7 +5,7 @@
  *	modify it under the terms of the GNU General Public License version
  *	2 as published by the Free Software Foundation.
  *
- *	2006.12.10 yhlu moved it to LinuxBIOS and use struct instead
+ *	2006.12.10 yhlu moved it to corbeoot and use struct instead
  */
 #ifndef __ROMCC__
 #include <console/console.h>
diff --git a/src/lib/version.c b/src/lib/version.c
index 028e0062b2..404f50d730 100644
--- a/src/lib/version.c
+++ b/src/lib/version.c
@@ -7,52 +7,52 @@
 #error  MAINBOARD_PART_NUMBER not defined
 #endif
 
-#ifndef LINUXBIOS_VERSION
-#error  LINUXBIOS_VERSION not defined
+#ifndef COREBOOT_VERSION
+#error  COREBOOT_VERSION not defined
 #endif
-#ifndef LINUXBIOS_BUILD
-#error  LINUXBIOS_BUILD not defined
+#ifndef COREBOOT_BUILD
+#error  COREBOOT_BUILD not defined
 #endif
 
-#ifndef LINUXBIOS_COMPILE_TIME
-#error  LINUXBIOS_COMPILE_TIME not defined
+#ifndef COREBOOT_COMPILE_TIME
+#error  COREBOOT_COMPILE_TIME not defined
 #endif
-#ifndef LINUXBIOS_COMPILE_BY
-#error  LINUXBIOS_COMPILE_BY not defined
+#ifndef COREBOOT_COMPILE_BY
+#error  COREBOOT_COMPILE_BY not defined
 #endif
-#ifndef LINUXBIOS_COMPILE_HOST
-#error  LINUXBIOS_COMPILE_HOST not defined
+#ifndef COREBOOT_COMPILE_HOST
+#error  COREBOOT_COMPILE_HOST not defined
 #endif
 
-#ifndef LINUXBIOS_COMPILER
-#error  LINUXBIOS_COMPILER not defined
+#ifndef COREBOOT_COMPILER
+#error  COREBOOT_COMPILER not defined
 #endif
-#ifndef LINUXBIOS_LINKER
-#error  LINUXBIOS_LINKER not defined
+#ifndef COREBOOT_LINKER
+#error  COREBOOT_LINKER not defined
 #endif
-#ifndef LINUXBIOS_ASSEMBLER
-#error  LINUXBIOS_ASSEMBLER not defined
+#ifndef COREBOOT_ASSEMBLER
+#error  COREBOOT_ASSEMBLER not defined
 #endif
 
 
-#ifndef  LINUXBIOS_EXTRA_VERSION
-#define LINUXBIOS_EXTRA_VERSION ""
+#ifndef  COREBOOT_EXTRA_VERSION
+#define COREBOOT_EXTRA_VERSION ""
 #endif
 
 const char mainboard_vendor[] = MAINBOARD_VENDOR;
 const char mainboard_part_number[] = MAINBOARD_PART_NUMBER;
 
-const char linuxbios_version[] = LINUXBIOS_VERSION;
-const char linuxbios_extra_version[] = LINUXBIOS_EXTRA_VERSION;
-const char linuxbios_build[] = LINUXBIOS_BUILD;
-
-const char linuxbios_compile_time[]   = LINUXBIOS_COMPILE_TIME;
-const char linuxbios_compile_by[]     = LINUXBIOS_COMPILE_BY;
-const char linuxbios_compile_host[]   = LINUXBIOS_COMPILE_HOST;
-const char linuxbios_compile_domain[] = LINUXBIOS_COMPILE_DOMAIN;
-const char linuxbios_compiler[]       = LINUXBIOS_COMPILER;
-const char linuxbios_linker[]         = LINUXBIOS_LINKER;
-const char linuxbios_assembler[]      = LINUXBIOS_ASSEMBLER;
+const char coreboot_version[] = COREBOOT_VERSION;
+const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION;
+const char coreboot_build[] = COREBOOT_BUILD;
+
+const char coreboot_compile_time[]   = COREBOOT_COMPILE_TIME;
+const char coreboot_compile_by[]     = COREBOOT_COMPILE_BY;
+const char coreboot_compile_host[]   = COREBOOT_COMPILE_HOST;
+const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN;
+const char coreboot_compiler[]       = COREBOOT_COMPILER;
+const char coreboot_linker[]         = COREBOOT_LINKER;
+const char coreboot_assembler[]      = COREBOOT_ASSEMBLER;
 
 
 
diff --git a/src/mainboard/a-trend/atc-6220/Options.lb b/src/mainboard/a-trend/atc-6220/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/a-trend/atc-6220/Options.lb
+++ b/src/mainboard/a-trend/atc-6220/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb
index 3c8d9b133e..b8199f1a54 100644
--- a/src/mainboard/advantech/pcm-5820/Options.lb
+++ b/src/mainboard/advantech/pcm-5820/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/agami/aruma/Config.lb b/src/mainboard/agami/aruma/Config.lb
index c8cdcd8bd5..b327bf651f 100644
--- a/src/mainboard/agami/aruma/Config.lb
+++ b/src/mainboard/agami/aruma/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -145,7 +145,7 @@ else
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 mainboardinit cpu/x86/16bit/entry16.inc
@@ -163,7 +163,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -193,7 +193,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/agami/aruma/Options.lb b/src/mainboard/agami/aruma/Options.lb
index 04fff60e3b..47eb59fa7f 100644
--- a/src/mainboard/agami/aruma/Options.lb
+++ b/src/mainboard/agami/aruma/Options.lb
@@ -37,7 +37,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CC
 uses HOSTCC
@@ -140,7 +140,7 @@ default ACPI_SSDTX_NUM=3
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -196,10 +196,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0
 
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -218,7 +218,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -262,7 +262,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
@@ -275,7 +275,7 @@ default TTYS0_LCS=0x3
 ## SPEW       9   Way too many details             
 
 
-## These values can be overwritten by LinuxBIOSv2/targets/agami/aruma/Config.lb
+## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb
 ## Request this level of debugging output
 default  DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
diff --git a/src/mainboard/agami/aruma/acpi_tables_static.c b/src/mainboard/agami/aruma/acpi_tables_static.c
index 3ff0d717c9..b20a7d72e5 100644
--- a/src/mainboard/agami/aruma/acpi_tables_static.c
+++ b/src/mainboard/agami/aruma/acpi_tables_static.c
@@ -83,7 +83,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 /* The next two tables are used by our DSDT and are freely defined
  * here. This construct is used because the bus numbers containing 
- * the 8131 bridges may vary so that we need to pass LinuxBIOS 
+ * the 8131 bridges may vary so that we need to pass coreboot 
  * knowledge into the DSDT
  */
 typedef struct lnxc_busses {
@@ -96,7 +96,7 @@ typedef struct acpi_lnxb {
 	acpi_lnxb_busses_t busses[5];
 } acpi_lnxb_t;
 
-/* special linuxbios acpi table */
+/* special coreboot acpi table */
 void acpi_create_lnxb(acpi_lnxb_t *lnxb)
 {
 	device_t dev;
diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb
index 975def30c0..56dd3f67e1 100644
--- a/src/mainboard/amd/db800/Config.lb
+++ b/src/mainboard/amd/db800/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE			= ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE	  = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -62,7 +62,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -70,7 +70,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -90,7 +90,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb
index ea0e708feb..6a0dc3f8c0 100644
--- a/src/mainboard/amd/db800/Options.lb
+++ b/src/mainboard/amd/db800/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -92,10 +92,10 @@ default IRQ_SLOT_COUNT=4
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -158,7 +158,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb
index 24fc3f46b4..a7cf5552e9 100644
--- a/src/mainboard/amd/norwich/Config.lb
+++ b/src/mainboard/amd/norwich/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE			= ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE	  = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -64,7 +64,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -72,7 +72,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -92,7 +92,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb
index d549c9688e..0d4b2239ff 100644
--- a/src/mainboard/amd/norwich/Options.lb
+++ b/src/mainboard/amd/norwich/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -92,10 +92,10 @@ default IRQ_SLOT_COUNT=6
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -158,7 +158,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb
index ffa06d5e09..f7a9616693 100644
--- a/src/mainboard/amd/rumba/Config.lb
+++ b/src/mainboard/amd/rumba/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/amd/rumba/Options.lb b/src/mainboard/amd/rumba/Options.lb
index 0d44ee1864..e929289261 100644
--- a/src/mainboard/amd/rumba/Options.lb
+++ b/src/mainboard/amd/rumba/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -60,7 +60,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -82,10 +82,10 @@ default IRQ_SLOT_COUNT=2
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -141,7 +141,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
index f54c423fbd..6948a70948 100644
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -154,7 +154,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 if HAVE_FAILOVER_BOOT
@@ -181,7 +181,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -215,7 +215,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb
index 0b2f24e991..9cdc29dac9 100644
--- a/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Options.lb
@@ -40,7 +40,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -122,7 +122,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -149,7 +149,7 @@ default ACPI_SSDTX_NUM=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -237,10 +237,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -259,7 +259,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -309,7 +309,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index 2fb327daec..99a89f94e4 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -1,7 +1,7 @@
 At this time, For acpi support We got
-1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c)
-2. support MADT ---- dynamically (LinuxBIOS run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
-3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
+1. support AMK K8 SRAT --- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c)
+2. support MADT ---- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
+3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
 4. Chipset support: amd8111, amd8132
 
 The developers need to change for different MB
@@ -11,7 +11,7 @@ Change dx/dsdt_lb.dsl, according to MB layout
 	if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
 
 Change acpi_tables.c
-	sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents.  ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now.
+	sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents.  ---- Actually you don't need to change it, it is coreboot run-time configurable now.
 	if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
 
 Regarding pci bridge apic and pic
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
index ac7375a6ae..ec46406291 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
@@ -19,7 +19,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -36,18 +36,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE		 = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -163,7 +163,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 if HAVE_FAILOVER_BOOT
@@ -190,7 +190,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -225,7 +225,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index cb68daa181..1382aa2d55 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -147,7 +147,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -174,7 +174,7 @@ default ACPI_SSDTX_NUM=31
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -261,10 +261,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -283,7 +283,7 @@ default HEAP_SIZE=0xc0000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00200000
 
@@ -334,7 +334,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index 68a3f56788..3c4804ace0 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -91,7 +91,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -111,7 +111,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -141,7 +141,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
index 9f712b883f..adb5f601bd 100644
--- a/src/mainboard/arima/hdama/Options.lb
+++ b/src/mainboard/arima/hdama/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -82,7 +82,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -104,7 +104,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -145,10 +145,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -167,7 +167,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -216,7 +216,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb
index 40f157f6e9..58c833ea95 100644
--- a/src/mainboard/artecgroup/dbe61/Config.lb
+++ b/src/mainboard/artecgroup/dbe61/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -60,7 +60,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -68,7 +68,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -88,7 +88,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb
index 3f773af79c..d95f0a9bf7 100644
--- a/src/mainboard/artecgroup/dbe61/Options.lb
+++ b/src/mainboard/artecgroup/dbe61/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -93,10 +93,10 @@ default IRQ_SLOT_COUNT=3
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -159,7 +159,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/artecgroup/dbe61/realmode/vgabios.c b/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
index 9f3b28d5b7..ac9c1bdf02 100644
--- a/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
+++ b/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
@@ -66,7 +66,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used 
-   without reliance on other parts of core Linuxbios 
+   without reliance on other parts of core coreboot 
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -442,10 +442,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords, 
 // and pop to protected mode. 
-// second, since this only ever runs as part of linuxbios, 
+// second, since this only ever runs as part of coreboot, 
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to 
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler_vga(void)
@@ -921,7 +921,7 @@ static void vga_init(device_t dev)
 
 	pci_dev_init(dev);
 
-	// code to make vga init run in real mode - does work but against the current Linuxbios philosophy 
+	// code to make vga init run in real mode - does work but against the current coreboot philosophy 
     printk_debug("INSTALL REAL-MODE IDT\n");
     setup_realmode_idt();
     printk_debug("DO THE VGA BIOS\n");
diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb
index 74597a967f..fdf8f83097 100644
--- a/src/mainboard/asi/mb_5blmp/Config.lb
+++ b/src/mainboard/asi/mb_5blmp/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -71,7 +71,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -79,7 +79,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -99,7 +99,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb
index 51e8dcdc75..c1bf6cd517 100644
--- a/src/mainboard/asi/mb_5blmp/Options.lb
+++ b/src/mainboard/asi/mb_5blmp/Options.lb
@@ -7,7 +7,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -57,7 +57,7 @@ default ROM_SIZE = 256 * 1024
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -78,10 +78,10 @@ default IRQ_SLOT_COUNT=5        # TODO?
 # default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 64 * 1024
 default FALLBACK_SIZE = 128 * 1024
 
@@ -137,7 +137,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb
index db635e52d4..07a7ade1aa 100644
--- a/src/mainboard/asus/a8n_e/Config.lb
+++ b/src/mainboard/asus/a8n_e/Config.lb
@@ -23,7 +23,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -39,18 +39,18 @@ else
 end
 
 ##
-## Compute the start location and size size of the LinuxBIOS bootloader.
+## Compute the start location and size size of the coreboot bootloader.
 ##
 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of LinuxBIOS will start in the boot ROM.
+## Compute where this copy of coreboot will start in the boot ROM.
 ##
 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can be cached to speed up LinuxBIOS
+## Compute a range of ROM that can be cached to speed up coreboot
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte)
@@ -106,7 +106,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our 16 bit and 32 bit LinuxBIOS entry code.
+## Build our 16 bit and 32 bit coreboot entry code.
 ##
 if HAVE_FAILOVER_BOOT
 	if USE_FAILOVER_IMAGE
@@ -130,7 +130,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (this is where LinuxBIOS is entered).
+## Build our reset vector (this is where coreboot is entered).
 ##
 if HAVE_FAILOVER_BOOT
 	if USE_FAILOVER_IMAGE
@@ -186,7 +186,7 @@ end
 
 
 ###
-### This is the early phase of LinuxBIOS startup.
+### This is the early phase of coreboot startup.
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb
index 392c0bc1b4..e4eef79986 100644
--- a/src/mainboard/asus/a8n_e/Options.lb
+++ b/src/mainboard/asus/a8n_e/Options.lb
@@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -127,7 +127,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -149,7 +149,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -223,10 +223,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = (64*1024)
 #65536
 
@@ -247,7 +247,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -296,7 +296,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb
index a8b1a1c3bc..e95511a647 100644
--- a/src/mainboard/asus/a8v-e_se/Config.lb
+++ b/src/mainboard/asus/a8v-e_se/Config.lb
@@ -23,7 +23,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
     if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -35,19 +35,19 @@
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -97,7 +97,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 if USE_FALLBACK_IMAGE
@@ -122,7 +122,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 
 if USE_FALLBACK_IMAGE 
@@ -141,7 +141,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb
index 6c57edecdb..b6c5cea799 100644
--- a/src/mainboard/asus/a8v-e_se/Options.lb
+++ b/src/mainboard/asus/a8v-e_se/Options.lb
@@ -56,7 +56,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -121,7 +121,7 @@ default FALLBACK_SIZE=256 * 1024
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -143,7 +143,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=0
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -217,10 +217,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1043
 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 64 * 1024
 
 ##
@@ -242,7 +242,7 @@ default HEAP_SIZE=256 * 1024
 ##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -291,7 +291,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb
index b02013191d..d4cf5e307f 100644
--- a/src/mainboard/asus/mew-am/Options.lb
+++ b/src/mainboard/asus/mew-am/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb
index ade4ffd1ec..76a74a3425 100644
--- a/src/mainboard/asus/mew-vm/Config.lb
+++ b/src/mainboard/asus/mew-vm/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb
index 3f8775f2e6..da63cffd9e 100644
--- a/src/mainboard/asus/mew-vm/Options.lb
+++ b/src/mainboard/asus/mew-vm/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -60,7 +60,7 @@ default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET = 0
 
@@ -79,10 +79,10 @@ default HAVE_OPTION_TABLE = 0
 default CONFIG_IDE = 1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -138,7 +138,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/asus/p2b-f/Options.lb
+++ b/src/mainboard/asus/p2b-f/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb
index 8653db38aa..4038c3c7d5 100644
--- a/src/mainboard/asus/p2b/Options.lb
+++ b/src/mainboard/asus/p2b/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/asus/p3b-f/Options.lb
+++ b/src/mainboard/asus/p3b-f/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb
index 15cf5acd82..36fde166bc 100644
--- a/src/mainboard/axus/tc320/Options.lb
+++ b/src/mainboard/axus/tc320/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/axus/tc320/irq_tables.c b/src/mainboard/axus/tc320/irq_tables.c
index c5ac51861d..8a8ada270a 100644
--- a/src/mainboard/axus/tc320/irq_tables.c
+++ b/src/mainboard/axus/tc320/irq_tables.c
@@ -24,7 +24,7 @@
  * It was not possible to read back the PIRQ table. There was no BIOS to ask
  * for it, only a bootloader for an embedded OS.
  * But with the method described here:
- *    http://linuxbios.org/Creating_Valid_IRQ_Tables
+ *    http://coreboot.org/Creating_Valid_IRQ_Tables
  * it was possible to detect the physical IRQ routing on this board.
  *
  * This is the physical routing on this board:
diff --git a/src/mainboard/azza/pt-6ibd/Options.lb b/src/mainboard/azza/pt-6ibd/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/azza/pt-6ibd/Options.lb
+++ b/src/mainboard/azza/pt-6ibd/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb
index 1d6d9e18ec..4e4e21fc25 100644
--- a/src/mainboard/bcom/winnet100/Options.lb
+++ b/src/mainboard/bcom/winnet100/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/biostar/m6tba/Options.lb b/src/mainboard/biostar/m6tba/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/biostar/m6tba/Options.lb
+++ b/src/mainboard/biostar/m6tba/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb
index c9a22ca523..37681996fb 100644
--- a/src/mainboard/broadcom/blast/Config.lb
+++ b/src/mainboard/broadcom/blast/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -72,7 +72,7 @@ if USE_DCACHE_RAM
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -88,7 +88,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -112,7 +112,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/broadcom/blast/Options.lb b/src/mainboard/broadcom/blast/Options.lb
index d02aa9796f..6142896092 100644
--- a/src/mainboard/broadcom/blast/Options.lb
+++ b/src/mainboard/broadcom/blast/Options.lb
@@ -36,7 +36,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -89,7 +89,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -111,7 +111,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -168,10 +168,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
 
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -190,7 +190,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -239,7 +239,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb
index af2133a739..6be46d3ed4 100644
--- a/src/mainboard/dell/s1850/Config.lb
+++ b/src/mainboard/dell/s1850/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -75,7 +75,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -83,7 +83,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -103,7 +103,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb
index d92a8fd0a3..369cbe542d 100644
--- a/src/mainboard/dell/s1850/Options.lb
+++ b/src/mainboard/dell/s1850/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
index 0888104513..7e6dcff573 100644
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ b/src/mainboard/digitallogic/adl855pc/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -69,7 +69,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -77,7 +77,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -97,7 +97,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb
index f4c9d0548d..547113475e 100644
--- a/src/mainboard/digitallogic/adl855pc/Options.lb
+++ b/src/mainboard/digitallogic/adl855pc/Options.lb
@@ -11,7 +11,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -57,7 +57,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -79,10 +79,10 @@ default IRQ_SLOT_COUNT=5
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb
index 2ea32e6ba0..bd3f1958d4 100644
--- a/src/mainboard/digitallogic/msm586seg/Config.lb
+++ b/src/mainboard/digitallogic/msm586seg/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 default ROM_SIZE = 512 * 1024 
 default FALLBACK_SIZE = 0x10000
@@ -14,18 +14,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -71,7 +71,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -79,7 +79,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -99,7 +99,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/digitallogic/msm586seg/Options.lb b/src/mainboard/digitallogic/msm586seg/Options.lb
index b87885271b..2b763438ae 100644
--- a/src/mainboard/digitallogic/msm586seg/Options.lb
+++ b/src/mainboard/digitallogic/msm586seg/Options.lb
@@ -12,7 +12,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -87,10 +87,10 @@ default IRQ_SLOT_COUNT=7
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb
index 6294701e4c..41fd678a90 100644
--- a/src/mainboard/digitallogic/msm800sev/Config.lb
+++ b/src/mainboard/digitallogic/msm800sev/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -61,7 +61,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -69,7 +69,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -89,7 +89,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb
index 8e2361b25a..cdab41a892 100644
--- a/src/mainboard/digitallogic/msm800sev/Options.lb
+++ b/src/mainboard/digitallogic/msm800sev/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -70,7 +70,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -92,10 +92,10 @@ default IRQ_SLOT_COUNT=6
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -158,7 +158,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
index 1282bd5554..6842f09a17 100644
--- a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
+++ b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
@@ -101,7 +101,7 @@ void cache_as_ram_main(void)
 		Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
 	 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
 		That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
-		as the rest of LinuxBIOS. If that is the case we can just do a wbinvd. The stack will be written into real
+		as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
 		RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
 		where LB would like it, you need to write some code to do a copy from cache to RAM
 
diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb
index e0ef7fdbdd..9ad29487ad 100644
--- a/src/mainboard/eaglelion/5bcm/Config.lb
+++ b/src/mainboard/eaglelion/5bcm/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb
index adc3d1b02a..280f582845 100644
--- a/src/mainboard/eaglelion/5bcm/Options.lb
+++ b/src/mainboard/eaglelion/5bcm/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -61,7 +61,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -83,10 +83,10 @@ default IRQ_SLOT_COUNT=2
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -142,7 +142,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb
index a47d1c6487..551eebca67 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Config.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb
@@ -23,5 +23,5 @@ end
 ## Build the objects we have code for in this directory.
 ##
 
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
+addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
 makedefine CFLAGS += -msoft-float
diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb
index c0aa4e0506..4078fb4144 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Options.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb
@@ -44,7 +44,7 @@ uses STACK_SIZE HEAP_SIZE
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -106,7 +106,7 @@ default ROM_SIZE=1048576
 ## Board has fixed size RAM
 default EMBEDDED_RAM_SIZE=64*1024*1024
 
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 default _RAMBASE=0x00100000
 
 ##
@@ -133,10 +133,10 @@ default _RESET=0xfffffffc
 ## Exception vectors
 default _EXCEPTION_VECTORS=_ROMBASE+0x100
 
-## linuxBIOS ROM start address
+## coreboot ROM start address
 default _ROMSTART=0xfff03000
 
-## linuxBIOS C code runs at this location in RAM
+## coreboot C code runs at this location in RAM
 default _RAMBASE=0x00100000
 
 ### End Options.lb
diff --git a/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg b/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
index 568efb8f6b..305245d751 100755
--- a/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
+++ b/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
@@ -62,7 +62,7 @@ SIO         2002 9600              ;TCP port for serial IO
 [HOST]
 IP          10.0.1.2
 FORMAT      ELF
-FILE        linuxbios.elf
+FILE        coreboot.elf
 ;START       0x200000
 LOAD        MANUAL              ;load code MANUAL or AUTO after reset
 DEBUGPORT   2001
diff --git a/src/mainboard/emulation/qemu-i386/Config.lb b/src/mainboard/emulation/qemu-i386/Config.lb
index 72253f7763..b2a009d2e5 100644
--- a/src/mainboard/emulation/qemu-i386/Config.lb
+++ b/src/mainboard/emulation/qemu-i386/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 default ROM_SIZE = 256 * 1024 
 default ROM_SECTION_SIZE   = ROM_SIZE
@@ -8,18 +8,18 @@ default ROM_SECTION_OFFSET = 0
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -66,7 +66,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -74,7 +74,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 mainboardinit cpu/x86/16bit/reset16.inc 
 ldscript /cpu/x86/16bit/reset16.lds 
diff --git a/src/mainboard/emulation/qemu-i386/Options.lb b/src/mainboard/emulation/qemu-i386/Options.lb
index 62a8ddd8d2..74e543f737 100644
--- a/src/mainboard/emulation/qemu-i386/Options.lb
+++ b/src/mainboard/emulation/qemu-i386/Options.lb
@@ -14,7 +14,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -63,7 +63,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -80,10 +80,10 @@ default IRQ_SLOT_COUNT=5
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/mainboard/emulation/qemu-i386/mainboard.c b/src/mainboard/emulation/qemu-i386/mainboard.c
index 0562799f16..cfbc0b2246 100644
--- a/src/mainboard/emulation/qemu-i386/mainboard.c
+++ b/src/mainboard/emulation/qemu-i386/mainboard.c
@@ -10,7 +10,7 @@ void vga_enable_console();
 
 static void vga_init(device_t dev)
 {
-	/* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */
+	/* code to make vga init run in real mode - does work but against the current coreboot philosophy */
 	printk_debug("INSTALL REAL-MODE IDT\n");
         setup_realmode_idt();
         printk_debug("DO THE VGA BIOS\n");
diff --git a/src/mainboard/emulation/qemu-i386/vgabios.c b/src/mainboard/emulation/qemu-i386/vgabios.c
index 072cb7f21c..7f42f0ab12 100644
--- a/src/mainboard/emulation/qemu-i386/vgabios.c
+++ b/src/mainboard/emulation/qemu-i386/vgabios.c
@@ -64,7 +64,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used 
-   without reliance on other parts of core Linuxbios 
+   without reliance on other parts of core coreboot 
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -398,10 +398,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords, 
 // and pop to protected mode. 
-// second, since this only ever runs as part of linuxbios, 
+// second, since this only ever runs as part of coreboot, 
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to 
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
diff --git a/src/mainboard/gigabyte/ga-6bxc/Options.lb b/src/mainboard/gigabyte/ga-6bxc/Options.lb
index df13ee490b..ce083410e4 100644
--- a/src/mainboard/gigabyte/ga-6bxc/Options.lb
+++ b/src/mainboard/gigabyte/ga-6bxc/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
index 6e17d29d30..d58363adaf 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
@@ -23,7 +23,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -40,18 +40,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -113,7 +113,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -141,7 +141,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -190,7 +190,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
index cde543e1ad..d91f2d1e80 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -64,7 +64,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -148,7 +148,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -173,7 +173,7 @@ default HAVE_ACPI_TABLES=0
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -259,10 +259,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -281,7 +281,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -333,7 +333,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
index 0f27a7ab44..93a012fb75 100644
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ b/src/mainboard/gigabyte/m57sli/Config.lb
@@ -21,7 +21,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -38,18 +38,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -111,7 +111,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -139,7 +139,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -188,7 +188,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb
index 91d08f04c5..149bbde94c 100644
--- a/src/mainboard/gigabyte/m57sli/Options.lb
+++ b/src/mainboard/gigabyte/m57sli/Options.lb
@@ -62,7 +62,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -146,7 +146,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -171,7 +171,7 @@ default HAVE_ACPI_TABLES=0
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -257,10 +257,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -279,7 +279,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -331,7 +331,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb
index 35d2273aea..a63f1f684e 100644
--- a/src/mainboard/ibm/e325/Config.lb
+++ b/src/mainboard/ibm/e325/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -92,7 +92,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -112,7 +112,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -142,7 +142,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb
index f8c4344645..21fc57a453 100644
--- a/src/mainboard/ibm/e325/Options.lb
+++ b/src/mainboard/ibm/e325/Options.lb
@@ -32,7 +32,7 @@ uses LB_CKS_LOC
 uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -71,7 +71,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -93,7 +93,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -129,10 +129,10 @@ default MAINBOARD_VENDOR="IBM"
 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -151,7 +151,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -195,7 +195,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb
index 49a802bee7..9407ab51c5 100644
--- a/src/mainboard/ibm/e326/Config.lb
+++ b/src/mainboard/ibm/e326/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -92,7 +92,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -112,7 +112,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -142,7 +142,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/ibm/e326/Options.lb b/src/mainboard/ibm/e326/Options.lb
index d2e5cf488f..40db181ab5 100644
--- a/src/mainboard/ibm/e326/Options.lb
+++ b/src/mainboard/ibm/e326/Options.lb
@@ -32,7 +32,7 @@ uses LB_CKS_LOC
 uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -73,7 +73,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -95,7 +95,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -135,10 +135,10 @@ default MAINBOARD_VENDOR="IBM"
 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -157,7 +157,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -201,7 +201,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb
index 53b1982fd1..aac495186d 100644
--- a/src/mainboard/iei/juki-511p/Config.lb
+++ b/src/mainboard/iei/juki-511p/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 default ROM_SIZE = 256 * 1024 
 default ROM_SECTION_SIZE   = ROM_SIZE
@@ -8,18 +8,18 @@ default ROM_SECTION_OFFSET = 0
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -66,7 +66,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -74,7 +74,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 mainboardinit cpu/x86/16bit/reset16.inc 
 ldscript /cpu/x86/16bit/reset16.lds 
diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb
index e2185a2604..cd5be9cad3 100644
--- a/src/mainboard/iei/juki-511p/Options.lb
+++ b/src/mainboard/iei/juki-511p/Options.lb
@@ -15,7 +15,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -62,7 +62,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -80,10 +80,10 @@ default IRQ_SLOT_COUNT=2
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb
index 121e468bd2..3b4094a25f 100644
--- a/src/mainboard/iei/nova4899r/Config.lb
+++ b/src/mainboard/iei/nova4899r/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb
index 771a40b379..778cf737fc 100644
--- a/src/mainboard/iei/nova4899r/Options.lb
+++ b/src/mainboard/iei/nova4899r/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -68,7 +68,7 @@ default HAVE_FALLBACK_BOOT=0
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -90,10 +90,10 @@ default IRQ_SLOT_COUNT=7
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -149,7 +149,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
index 5cea22a5c7..5f0e697232 100644
--- a/src/mainboard/intel/jarrell/Config.lb
+++ b/src/mainboard/intel/jarrell/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -75,7 +75,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -83,7 +83,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -103,7 +103,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb
index abc11a5013..0bd5636c5a 100644
--- a/src/mainboard/intel/jarrell/Options.lb
+++ b/src/mainboard/intel/jarrell/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -88,7 +88,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -110,7 +110,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -139,10 +139,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -158,12 +158,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -213,7 +213,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb
index f03b9c4015..52efe0f326 100644
--- a/src/mainboard/intel/xe7501devkit/Config.lb
+++ b/src/mainboard/intel/xe7501devkit/Config.lb
@@ -2,7 +2,7 @@
 ## BEGIN BOILERPLATE - DO NOT EDIT
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus payload) will live in the boot rom chip.
+## (coreboot plus payload) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 # The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
@@ -11,7 +11,7 @@ if USE_FALLBACK_IMAGE
 	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
 
 else
-# The normal image goes at the beginning of the LinuxBIOS ROM region
+# The normal image goes at the beginning of the coreboot ROM region
 # and uses all the remaining space
 
 	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
@@ -19,12 +19,12 @@ else
 end
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -81,7 +81,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -89,7 +89,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FALLBACK_BOOT
     if USE_FALLBACK_IMAGE 
@@ -114,7 +114,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb
index 0595fe28e5..2f5a71d04c 100644
--- a/src/mainboard/intel/xe7501devkit/Options.lb
+++ b/src/mainboard/intel/xe7501devkit/Options.lb
@@ -55,7 +55,7 @@ uses USE_FALLBACK_IMAGE
 uses ROM_SIZE
 uses ROM_IMAGE_SIZE
 uses FALLBACK_SIZE
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 
 ## These are defined in mainboard Config.lb, don't add here
 uses ROM_SECTION_SIZE
@@ -143,7 +143,7 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
 ##
@@ -162,7 +162,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = 0
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -211,7 +211,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h
index 84661ddb36..2378ceaea0 100644
--- a/src/mainboard/intel/xe7501devkit/bus.h
+++ b/src/mainboard/intel/xe7501devkit/bus.h
@@ -1,7 +1,7 @@
 #ifndef XE7501DEVKIT_BUS_H_INCLUDED
 #define XE7501DEVKIT_BUS_H_INCLUDED
 
-// These were determined by seeing how LinuxBIOS enumerates the various
+// These were determined by seeing how coreboot enumerates the various
 // PCI (and PCI-like) buses on the board.
 
 #define PCI_BUS_CHIPSET		0
diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h
index 642c04519f..30ae8e7a73 100644
--- a/src/mainboard/intel/xe7501devkit/ioapic.h
+++ b/src/mainboard/intel/xe7501devkit/ioapic.h
@@ -1,4 +1,4 @@
-// IOAPIC addresses determined by LinuxBIOS enumeration. 
+// IOAPIC addresses determined by coreboot enumeration. 
 // Someday add functions to get APIC IDs and versions from the chips themselves.
 	
 #define IOAPIC_ICH3				2
diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb
index 31f3236d51..99ad24b981 100644
--- a/src/mainboard/iwill/dk8_htx/Config.lb
+++ b/src/mainboard/iwill/dk8_htx/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -162,7 +162,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 if HAVE_FAILOVER_BOOT
@@ -189,7 +189,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -223,7 +223,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb
index 713c8ad54d..6d8eab4d0c 100644
--- a/src/mainboard/iwill/dk8_htx/Options.lb
+++ b/src/mainboard/iwill/dk8_htx/Options.lb
@@ -40,7 +40,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -122,7 +122,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -149,7 +149,7 @@ default ACPI_SSDTX_NUM=3
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -236,10 +236,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -258,7 +258,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -308,7 +308,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb
index 59312df508..4cb18e5757 100644
--- a/src/mainboard/iwill/dk8s2/Config.lb
+++ b/src/mainboard/iwill/dk8s2/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -95,7 +95,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -115,7 +115,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -145,7 +145,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb
index 10e89d88b4..81aa84ef7e 100644
--- a/src/mainboard/iwill/dk8s2/Options.lb
+++ b/src/mainboard/iwill/dk8s2/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -72,7 +72,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -94,7 +94,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -131,10 +131,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -153,7 +153,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -202,7 +202,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb
index 30f7c3ce50..6eece3e320 100644
--- a/src/mainboard/iwill/dk8x/Config.lb
+++ b/src/mainboard/iwill/dk8x/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -92,7 +92,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -112,7 +112,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -142,7 +142,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb
index 4c982f2242..1811aa44c5 100644
--- a/src/mainboard/iwill/dk8x/Options.lb
+++ b/src/mainboard/iwill/dk8x/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -72,7 +72,7 @@ default FALLBACK_SIZE=131072
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -94,7 +94,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -130,10 +130,10 @@ default CONFIG_USE_INIT=0
 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -152,7 +152,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -201,7 +201,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb
index 3e3c521123..fc1f601951 100644
--- a/src/mainboard/lippert/frontrunner/Config.lb
+++ b/src/mainboard/lippert/frontrunner/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/lippert/frontrunner/Options.lb b/src/mainboard/lippert/frontrunner/Options.lb
index 0d44ee1864..e929289261 100644
--- a/src/mainboard/lippert/frontrunner/Options.lb
+++ b/src/mainboard/lippert/frontrunner/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -60,7 +60,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -82,10 +82,10 @@ default IRQ_SLOT_COUNT=2
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -141,7 +141,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb
index 7d42aa516c..ee6abf85fd 100644
--- a/src/mainboard/motorola/sandpoint/Config.lb
+++ b/src/mainboard/motorola/sandpoint/Config.lb
@@ -26,5 +26,5 @@ arch ppc end
 dir nvram
 dir flash
 
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
+addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
 makedefine CFLAGS += -g
diff --git a/src/mainboard/motorola/sandpoint/Options.lb b/src/mainboard/motorola/sandpoint/Options.lb
index b98ddb7ed3..85bd19bf5b 100644
--- a/src/mainboard/motorola/sandpoint/Options.lb
+++ b/src/mainboard/motorola/sandpoint/Options.lb
@@ -42,7 +42,7 @@ uses HEAP_SIZE
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -89,7 +89,7 @@ default CONFIG_FS_ISO9660=1
 default CONFIG_FS_FAT=1
 default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
-# LinuxBIOS must fit into 128KB
+# coreboot must fit into 128KB
 default ROM_IMAGE_SIZE=131072
 default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
 default PAYLOAD_SIZE=262144
@@ -108,11 +108,11 @@ default _RESET=_ROMBASE+0x100
 ## Exception vectors (other than reset vector)
 default _EXCEPTION_VECTORS=_RESET+0x100
 
-## Start of linuxBIOS in the boot rom
+## Start of coreboot in the boot rom
 ## = _RESET + exeception vector table size
 default _ROMSTART=_RESET+0x3100
 
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 default _RAMBASE=0x00100000
 default _RAMSTART=0x00100000
 
diff --git a/src/mainboard/motorola/sandpoint/sp7410.cfg b/src/mainboard/motorola/sandpoint/sp7410.cfg
index b5b8391ec8..95b96a5f0c 100644
--- a/src/mainboard/motorola/sandpoint/sp7410.cfg
+++ b/src/mainboard/motorola/sandpoint/sp7410.cfg
@@ -99,7 +99,7 @@ SIO         2002 9600
 [HOST]
 IP          10.0.1.11
 ;FILE        E:\cygnus\root\usr\demo\sp7400\vxworks
-FILE        linuxbios.elf
+FILE        coreboot.elf
 FORMAT      ELF
 ;START       0x403104
 LOAD        MANUAL        ;load code MANUAL or AUTO after reset
@@ -114,7 +114,7 @@ CHIPTYPE    AM29BX8     ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX
 CHIPSIZE    0x100000    ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
 BUSWIDTH    8           ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
 WORKSPACE   0x00000000  ;workspace in SDRAM
-FILE        linuxbios.elf
+FILE        coreboot.elf
 FORMAT      ELF
 ERASE       0xFFF00000  ;erase sector 0 of flash
 ERASE       0xFFF04000  ;erase sector 1 of flash
diff --git a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
index 80789df46b..5fcdcce805 100644
--- a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
+++ b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
@@ -39,7 +39,7 @@ uses HEAP_SIZE
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -86,7 +86,7 @@ default CONFIG_FS_ISO9660=1
 default CONFIG_FS_FAT=1
 default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
-# LinuxBIOS must fit into 128KB
+# coreboot must fit into 128KB
 default ROM_IMAGE_SIZE=131072
 default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
 default PAYLOAD_SIZE=262144
@@ -105,11 +105,11 @@ default _RESET=_ROMBASE+0x100
 ## Exception vectors (other than reset vector)
 default _EXCEPTION_VECTORS=_RESET+0x100
 
-## Start of linuxBIOS in the boot rom
+## Start of coreboot in the boot rom
 ## = _RESET + exeception vector table size
 default _ROMSTART=_RESET+0x3100
 
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 default _RAMBASE=0x00100000
 default _RAMSTART=0x00100000
 
diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb
index 72930615f6..85a659ba0a 100644
--- a/src/mainboard/msi/ms6178/Options.lb
+++ b/src/mainboard/msi/ms6178/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
index be426f3231..05473c97cf 100644
--- a/src/mainboard/msi/ms7260/Options.lb
+++ b/src/mainboard/msi/ms7260/Options.lb
@@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -121,7 +121,7 @@ default APIC_ID_OFFSET = 0x10
 default LIFT_BSP_APIC_ID = 1
 default CONFIG_CHIP_NAME = 1
 
-# Move the default LinuxBIOS CMOS range off of AMD RTC registers.
+# Move the default coreboot CMOS range off of AMD RTC registers.
 default LB_CKS_RANGE_START = 49
 default LB_CKS_RANGE_END = 122
 default LB_CKS_LOC = 123
diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb
index 445224a40e..856237fd55 100644
--- a/src/mainboard/msi/ms9185/Config.lb
+++ b/src/mainboard/msi/ms9185/Config.lb
@@ -24,7 +24,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -36,18 +36,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -98,7 +98,7 @@ if USE_DCACHE_RAM
        end
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 if USE_FALLBACK_IMAGE
@@ -118,7 +118,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
@@ -142,7 +142,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb
index 3229be329d..d42fb1515c 100644
--- a/src/mainboard/msi/ms9185/Options.lb
+++ b/src/mainboard/msi/ms9185/Options.lb
@@ -61,7 +61,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -131,7 +131,7 @@ default CONFIG_LB_MEM_TOPK=2048
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -158,7 +158,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -238,10 +238,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -260,7 +260,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -309,7 +309,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
index 05ef85795a..7c3a4e7ae9 100644
--- a/src/mainboard/msi/ms9282/Config.lb
+++ b/src/mainboard/msi/ms9282/Config.lb
@@ -24,7 +24,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -36,19 +36,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -122,7 +122,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -142,7 +142,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
@@ -180,7 +180,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
index 9e4b94d704..bef1e01f8c 100644
--- a/src/mainboard/msi/ms9282/Options.lb
+++ b/src/mainboard/msi/ms9282/Options.lb
@@ -57,7 +57,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -125,7 +125,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -147,7 +147,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -218,10 +218,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -240,7 +240,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -289,7 +289,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb
index 21e5b44a52..dd67de6a09 100644
--- a/src/mainboard/newisys/khepri/Config.lb
+++ b/src/mainboard/newisys/khepri/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -93,7 +93,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -113,7 +113,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -142,7 +142,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb
index f68f8a8bb5..0f5b3e7776 100644
--- a/src/mainboard/newisys/khepri/Options.lb
+++ b/src/mainboard/newisys/khepri/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -82,7 +82,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -104,7 +104,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -152,10 +152,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -174,7 +174,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -223,7 +223,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
index 4dcf75d774..34e2ae1725 100644
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Config.lb
@@ -21,7 +21,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -38,18 +38,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -142,7 +142,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -170,7 +170,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -219,7 +219,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
index 050e272560..7830dc7104 100644
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -62,7 +62,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -146,7 +146,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -171,7 +171,7 @@ default HAVE_ACPI_TABLES=0
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -257,10 +257,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -279,7 +279,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -331,7 +331,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/olpc/btest/Config.lb b/src/mainboard/olpc/btest/Config.lb
index a0add90240..889bee52cb 100644
--- a/src/mainboard/olpc/btest/Config.lb
+++ b/src/mainboard/olpc/btest/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/olpc/btest/Options.lb b/src/mainboard/olpc/btest/Options.lb
index 7d27ddc369..096a0ca6a7 100644
--- a/src/mainboard/olpc/btest/Options.lb
+++ b/src/mainboard/olpc/btest/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -61,7 +61,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -83,10 +83,10 @@ default IRQ_SLOT_COUNT=2
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -142,7 +142,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index a0add90240..889bee52cb 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/olpc/rev_a/Options.lb b/src/mainboard/olpc/rev_a/Options.lb
index 7d27ddc369..096a0ca6a7 100644
--- a/src/mainboard/olpc/rev_a/Options.lb
+++ b/src/mainboard/olpc/rev_a/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -61,7 +61,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -83,10 +83,10 @@ default IRQ_SLOT_COUNT=2
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -142,7 +142,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb
index 8c49d08f12..75e240af2f 100644
--- a/src/mainboard/pcengines/alix1c/Config.lb
+++ b/src/mainboard/pcengines/alix1c/Config.lb
@@ -20,7 +20,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -32,18 +32,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -81,7 +81,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -89,7 +89,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -109,7 +109,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/pcengines/alix1c/Options.lb b/src/mainboard/pcengines/alix1c/Options.lb
index ec73294a5d..3e5c0456cc 100644
--- a/src/mainboard/pcengines/alix1c/Options.lb
+++ b/src/mainboard/pcengines/alix1c/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -90,7 +90,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -111,10 +111,10 @@ default IRQ_SLOT_COUNT=5
 default HAVE_OPTION_TABLE=0
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
@@ -177,7 +177,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
index b4cd555fb4..a05e50a4d8 100644
--- a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
+++ b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
@@ -189,7 +189,7 @@ void cache_as_ram_main(void)
 	 * etc.  The stack might be used to return etc.  That means we
 	 * care about what is in the stack.  If we are smart we set
 	 * the CAR stack to the same location as the rest of
-	 * LinuxBIOS. If that is the case we can just do a wbinvd.
+	 * coreboot. If that is the case we can just do a wbinvd.
 	 * The stack will be written into real RAM that is now setup
 	 * and we continue like nothing happened.  If the stack is
 	 * located somewhere other than where LB would like it, you
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
index 82de7c3e1c..22c13e406e 100644
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ b/src/mainboard/sunw/ultra40/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -111,7 +111,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -151,7 +151,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb
index 7e62ae6aae..3c15841cf9 100644
--- a/src/mainboard/sunw/ultra40/Options.lb
+++ b/src/mainboard/sunw/ultra40/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID 
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -95,7 +95,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -117,7 +117,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -185,10 +185,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -207,7 +207,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -256,7 +256,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb
index 944e758735..4df0cc0547 100644
--- a/src/mainboard/supermicro/h8dmr/Config.lb
+++ b/src/mainboard/supermicro/h8dmr/Config.lb
@@ -21,7 +21,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -38,18 +38,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -111,7 +111,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -139,7 +139,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -188,7 +188,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb
index aedf1d0c11..a1104129a3 100644
--- a/src/mainboard/supermicro/h8dmr/Options.lb
+++ b/src/mainboard/supermicro/h8dmr/Options.lb
@@ -62,7 +62,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -145,7 +145,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -170,7 +170,7 @@ default HAVE_ACPI_TABLES=0
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -254,10 +254,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -276,7 +276,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -328,7 +328,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb
index fe04f33b86..668824f079 100644
--- a/src/mainboard/supermicro/x6dai_g/Config.lb
+++ b/src/mainboard/supermicro/x6dai_g/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can be cached to speed up linuxBIOS,
+## Compute a range of ROM that can be cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -75,7 +75,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -83,7 +83,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -103,7 +103,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb
index e40875a182..727f4dc4ab 100644
--- a/src/mainboard/supermicro/x6dai_g/Options.lb
+++ b/src/mainboard/supermicro/x6dai_g/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb
index 2ba628f574..366a061168 100644
--- a/src/mainboard/supermicro/x6dhe_g/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of LinuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE	=( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can be cached to speed up linuxBIOS.
+## Compute a range of ROM that can be cached to speed up coreboot.
 ## execution speed.
 ## XIP_ROM_SIZE must be a power of 2.
 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
@@ -74,7 +74,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -82,7 +82,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -102,7 +102,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb
index ebfe983951..e5c55bad58 100644
--- a/src/mainboard/supermicro/x6dhe_g/Options.lb
+++ b/src/mainboard/supermicro/x6dhe_g/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb
index 02999838eb..748cfde55c 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of LinuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE	=( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can be cached to speed up linuxBIOS.
+## Compute a range of ROM that can be cached to speed up coreboot.
 ## execution speed.
 ## XIP_ROM_SIZE must be a power of 2.
 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
@@ -74,7 +74,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -82,7 +82,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -102,7 +102,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb
index ebfe983951..e5c55bad58 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Options.lb
+++ b/src/mainboard/supermicro/x6dhe_g2/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb
index 31425bfaa5..abd07e71a8 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -75,7 +75,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -83,7 +83,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -103,7 +103,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb
index d92a8fd0a3..369cbe542d 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Options.lb
+++ b/src/mainboard/supermicro/x6dhr_ig/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
index 11df62618a..ad9b6d04e6 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
@@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -75,7 +75,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -83,7 +83,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
@@ -103,7 +103,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb
index d92a8fd0a3..369cbe542d 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb
+++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses _RAMBASE
@@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000
 
 ###
 ### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
+### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default FALLBACK_SIZE=131072
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb
index 82ccec988b..95dc2541e9 100644
--- a/src/mainboard/technologic/ts5300/Config.lb
+++ b/src/mainboard/technologic/ts5300/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 default ROM_SIZE = 128 * 1024 
 default FALLBACK_SIZE = 0x10000
@@ -14,18 +14,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -71,7 +71,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -79,7 +79,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -99,7 +99,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/technologic/ts5300/Options.lb b/src/mainboard/technologic/ts5300/Options.lb
index b1a74dde44..7334b8b7a6 100644
--- a/src/mainboard/technologic/ts5300/Options.lb
+++ b/src/mainboard/technologic/ts5300/Options.lb
@@ -12,7 +12,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -86,7 +86,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -103,10 +103,10 @@ default IRQ_SLOT_COUNT=7
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index ba91f2dfcb..968471c553 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -46,4 +46,4 @@ end
 ## Build the objects we have code for in this directory.
 ##
 
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
+addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb
index a9396d8d45..f3a08afd6b 100644
--- a/src/mainboard/totalimpact/briq/Options.lb
+++ b/src/mainboard/totalimpact/briq/Options.lb
@@ -39,7 +39,7 @@ uses CONFIG_SYS_CLK_FREQ
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -108,11 +108,11 @@ default _RESET=_ROMBASE+0x100
 ## Exception vectors (other than reset vector)
 default _EXCEPTION_VECTORS=_RESET+0x100
 
-## Start of linuxBIOS in the boot rom
+## Start of coreboot in the boot rom
 ## = _RESET + exeception vector table size
 default _ROMSTART=_RESET+0x3100
 
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 default _RAMBASE=0x00100000
 default _RAMSTART=0x00100000
 
diff --git a/src/mainboard/totalimpact/briq/briQ7400.cfg b/src/mainboard/totalimpact/briq/briQ7400.cfg
index 20a438703e..22c64f7c77 100644
--- a/src/mainboard/totalimpact/briq/briQ7400.cfg
+++ b/src/mainboard/totalimpact/briq/briQ7400.cfg
@@ -148,7 +148,7 @@ CHIPTYPE    AM29F     ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16
 CHIPSIZE    0x100000    ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
 BUSWIDTH    8           ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
 ;WORKSPACE   0x00000000  ;workspace in SDRAM
-FILE        linuxbios.rom
+FILE        coreboot.rom
 FORMAT      ELF
 ERASE       0xFFF00000  ;erase sector 0 of flash
 ERASE       0xFFF10000  ;erase sector 1 of flash
diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb
index 340325f42d..b0fa5250d2 100644
--- a/src/mainboard/tyan/s1846/Options.lb
+++ b/src/mainboard/tyan/s1846/Options.lb
@@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index 46f1b3821f..2506906222 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -107,7 +107,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -137,7 +137,7 @@ mainboardinit cpu/x86/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
index e151c7ed92..447b5513ea 100644
--- a/src/mainboard/tyan/s2735/Options.lb
+++ b/src/mainboard/tyan/s2735/Options.lb
@@ -36,7 +36,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -87,7 +87,7 @@ default FALLBACK_SIZE=131072
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -114,7 +114,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -162,10 +162,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -184,7 +184,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -233,7 +233,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2735/cache_as_ram_auto.c b/src/mainboard/tyan/s2735/cache_as_ram_auto.c
index 80af842f4f..797ff62b80 100644
--- a/src/mainboard/tyan/s2735/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2735/cache_as_ram_auto.c
@@ -259,7 +259,7 @@ cpu_reset_x:
                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 #endif
 	
-		/*copy and execute linuxbios_ram */
+		/*copy and execute coreboot_ram */
 		copy_and_run(new_cpu_reset);
 		/* We will not return */
 	}
diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb
index e6ca2c304b..3c0c7d2d96 100644
--- a/src/mainboard/tyan/s2850/Config.lb
+++ b/src/mainboard/tyan/s2850/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -110,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb
index d3f95014f3..cf1298e9c8 100644
--- a/src/mainboard/tyan/s2850/Options.lb
+++ b/src/mainboard/tyan/s2850/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -83,7 +83,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -105,7 +105,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -175,7 +175,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -224,7 +224,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb
index 4f1c6e4658..74a71f15a1 100644
--- a/src/mainboard/tyan/s2875/Config.lb
+++ b/src/mainboard/tyan/s2875/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -110,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb
index 189ca08b7d..b90d4184e2 100644
--- a/src/mainboard/tyan/s2875/Options.lb
+++ b/src/mainboard/tyan/s2875/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -84,7 +84,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -106,7 +106,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -154,10 +154,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -176,7 +176,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -225,7 +225,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb
index bd4289ff56..1bc7726788 100644
--- a/src/mainboard/tyan/s2880/Config.lb
+++ b/src/mainboard/tyan/s2880/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -110,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb
index d0efa27fa4..72c40d9466 100644
--- a/src/mainboard/tyan/s2880/Options.lb
+++ b/src/mainboard/tyan/s2880/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -83,7 +83,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -105,7 +105,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -175,7 +175,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -224,7 +224,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb
index 05ff5c7234..e1c42de929 100644
--- a/src/mainboard/tyan/s2881/Config.lb
+++ b/src/mainboard/tyan/s2881/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -110,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb
index 49599aeeef..edefbbe95e 100644
--- a/src/mainboard/tyan/s2881/Options.lb
+++ b/src/mainboard/tyan/s2881/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -88,7 +88,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -110,7 +110,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -170,10 +170,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -192,7 +192,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -241,7 +241,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb
index 10363604ae..d883177fcc 100644
--- a/src/mainboard/tyan/s2882/Config.lb
+++ b/src/mainboard/tyan/s2882/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -110,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb
index 1fb5694559..23b2658ed6 100644
--- a/src/mainboard/tyan/s2882/Options.lb
+++ b/src/mainboard/tyan/s2882/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -83,7 +83,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -105,7 +105,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -175,7 +175,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -224,7 +224,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index 795485df6d..a6c0449290 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -110,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -140,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
index 4d339d7e93..254483d3ad 100644
--- a/src/mainboard/tyan/s2885/Options.lb
+++ b/src/mainboard/tyan/s2885/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -94,7 +94,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -116,7 +116,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -180,10 +180,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -202,7 +202,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -251,7 +251,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
index 9c14f7d3ad..840d2703a6 100644
--- a/src/mainboard/tyan/s2891/Config.lb
+++ b/src/mainboard/tyan/s2891/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -98,7 +98,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -119,7 +119,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -157,7 +157,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb
index 484c84ecbe..8513e049fb 100644
--- a/src/mainboard/tyan/s2891/Options.lb
+++ b/src/mainboard/tyan/s2891/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -101,7 +101,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -123,7 +123,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -189,10 +189,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -211,7 +211,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -260,7 +260,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb
index 0c3e2ae8a4..14b320075d 100644
--- a/src/mainboard/tyan/s2892/Config.lb
+++ b/src/mainboard/tyan/s2892/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -98,7 +98,7 @@ end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -118,7 +118,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -156,7 +156,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb
index 8646e0a04b..9dbaf9dd31 100644
--- a/src/mainboard/tyan/s2892/Options.lb
+++ b/src/mainboard/tyan/s2892/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -94,7 +94,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -116,7 +116,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -176,10 +176,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -198,7 +198,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -247,7 +247,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index f24b07d5cb..f43ad82c4b 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -102,7 +102,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -130,7 +130,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -185,7 +185,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
index c27999a383..84922a399a 100644
--- a/src/mainboard/tyan/s2895/Options.lb
+++ b/src/mainboard/tyan/s2895/Options.lb
@@ -38,7 +38,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID 
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -106,7 +106,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -128,7 +128,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -197,10 +197,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -219,7 +219,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -268,7 +268,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb
index 6cb3491c0b..a92478a805 100644
--- a/src/mainboard/tyan/s2912/Config.lb
+++ b/src/mainboard/tyan/s2912/Config.lb
@@ -21,7 +21,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
 	default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -38,18 +38,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -112,7 +112,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -140,7 +140,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -189,7 +189,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb
index 09b647e00b..3326cdb15b 100644
--- a/src/mainboard/tyan/s2912/Options.lb
+++ b/src/mainboard/tyan/s2912/Options.lb
@@ -62,7 +62,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -146,7 +146,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -173,7 +173,7 @@ default ACPI_SSDTX_NUM=3
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -259,10 +259,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -281,7 +281,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00100000
 
@@ -333,7 +333,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb
index df44242896..c529a8a3c3 100644
--- a/src/mainboard/tyan/s4880/Config.lb
+++ b/src/mainboard/tyan/s4880/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -100,7 +100,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -121,7 +121,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -152,7 +152,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb
index 7afffb2c59..7024d629f4 100644
--- a/src/mainboard/tyan/s4880/Options.lb
+++ b/src/mainboard/tyan/s4880/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -87,7 +87,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -109,7 +109,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -162,10 +162,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -184,7 +184,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -233,7 +233,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb
index d128842c28..041dbb9748 100644
--- a/src/mainboard/tyan/s4882/Config.lb
+++ b/src/mainboard/tyan/s4882/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,19 +12,19 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -100,7 +100,7 @@ else
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -121,7 +121,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -152,7 +152,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb
index 08444d46b7..d95b1e3e35 100644
--- a/src/mainboard/tyan/s4882/Options.lb
+++ b/src/mainboard/tyan/s4882/Options.lb
@@ -35,7 +35,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -87,7 +87,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -109,7 +109,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -161,10 +161,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -183,7 +183,7 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00002000
 
@@ -232,7 +232,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
index a3e4b41486..c8537e0425 100644
--- a/src/mainboard/via/epia-m/Config.lb
+++ b/src/mainboard/via/epia-m/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -76,7 +76,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -84,7 +84,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -104,7 +104,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb
index 5c88e5f817..575cc5eeb3 100644
--- a/src/mainboard/via/epia-m/Options.lb
+++ b/src/mainboard/via/epia-m/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -71,7 +71,7 @@ default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -94,10 +94,10 @@ default HAVE_ACPI_TABLES=1
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/mainboard/via/epia-m/acpi_tables.c b/src/mainboard/via/epia-m/acpi_tables.c
index 209434415b..fbe859d3d2 100644
--- a/src/mainboard/via/epia-m/acpi_tables.c
+++ b/src/mainboard/via/epia-m/acpi_tables.c
@@ -1,5 +1,5 @@
 /*
- * LinuxBIOS ACPI Table support
+ * coreboot ACPI Table support
  * written by Stefan Reinauer <stepan@openbios.org>
  * ACPI FADT, FACS, and DSDT table support added by 
  * Nick Barker <nick.barker9@btinternet.com>, and those portions
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
index d48330ff4b..8f2ee10f02 100644
--- a/src/mainboard/via/epia-m/mainboard.c
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -13,7 +13,7 @@ static void vga_fixup(void) {
         // we do this right here because:
         // - all the hardware is working, and some VGA bioses seem to need
         //   that
-        // - we need page 0 below for linuxbios tables.
+        // - we need page 0 below for coreboot tables.
 
         printk_debug("INSTALL REAL-MODE IDT\n");
         setup_realmode_idt();
diff --git a/src/mainboard/via/epia-m/vgabios.c b/src/mainboard/via/epia-m/vgabios.c
index 8565ba2236..6d588a7021 100644
--- a/src/mainboard/via/epia-m/vgabios.c
+++ b/src/mainboard/via/epia-m/vgabios.c
@@ -66,7 +66,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used 
-   without reliance on other parts of core Linuxbios 
+   without reliance on other parts of core coreboot 
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -399,10 +399,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords, 
 // and pop to protected mode. 
-// second, since this only ever runs as part of linuxbios, 
+// second, since this only ever runs as part of coreboot, 
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to 
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index 4dc9511990..9c354f7350 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -69,7 +69,7 @@ makerule ./auto.inc
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -77,7 +77,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -97,7 +97,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb
index 218f20d86a..d58be818b1 100644
--- a/src/mainboard/via/epia/Options.lb
+++ b/src/mainboard/via/epia/Options.lb
@@ -20,7 +20,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -82,7 +82,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_MP_TABLE=0
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=0
 
@@ -107,10 +107,10 @@ default IRQ_SLOT_COUNT=5
 default HAVE_OPTION_TABLE=1
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 029e5e7a6d..d3fb11e349 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1019,7 +1019,7 @@ struct nodes_info_t {
 	u32 up_planes; // down planes will be [up_planes, planes)
 } __attribute__((packed));
 
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by linuxbios_car and linuxbios_ram stage. and linuxbios_ram may be running at 64bit later.*/
+/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
 #if CONFIG_AMDMCT == 0
 
 //#define MEM_CS_COPY 1
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index e9abb0bb06..249388b04a 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -206,14 +206,14 @@ u32 CALLCONV AmdRotateLeft(u32 value, u8 size, u32 count)
 
 void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value)
 {
-	/* Use LinuxBIOS PCI functions */
+	/* Use coreboot PCI functions */
 	*Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc));
 }
 
 
 void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value)
 {
-	/* Use LinuxBIOS PCI functions */
+	/* Use coreboot PCI functions */
 	pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value);
 }
 
diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h
index a8b7b5c1c9..1f6fc0f9fb 100644
--- a/src/northbridge/amd/amdht/comlib.h
+++ b/src/northbridge/amd/amdht/comlib.h
@@ -26,7 +26,7 @@
 
 #include "porting.h"
 
-/* include LinuxBIOS pci functions */
+/* include coreboot pci functions */
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 09953da2c4..aaf67a47a7 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -124,7 +124,7 @@ void getAmdTopolist(u8 ***p)
 /**
  * void amd_ht_init(struct sys_info *sysinfo)
  *
- *  AMD HT init LinuxBIOS wrapper
+ *  AMD HT init coreboot wrapper
  *
  */
 void amd_ht_init(struct sys_info *sysinfo)
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 757acba7d7..1b5af6864f 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -2003,7 +2003,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
 		train_ram(nodeid, sysinfo, sysinfox);
 	#else
 		/* Can copy dqs_timing to ap cache and run from cache?
-		* we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ?
+		* we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ?
 		*/
 		copy_and_run_ap_code_in_car(retcall);
 		// will go back by jump
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index c0839d2a88..d39bfcc8b2 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -75,7 +75,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	 Set default values for CPU registers
 	======================================================================*/
 
-	/* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because
+	/* NOTE : For coreboot, we don't need to set mtrr enables here because
 	they are still enable from cache_as_ram.inc */
 
 	addr = 0x250;
@@ -88,7 +88,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	/*======================================================================
 	  Set variable MTRR values
 	 ======================================================================*/
-	/* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using
+	/* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using
 		0x200, 0x201 for [1M, CONFIG_TOP_MEM)
 		0x202, 0x203 for ROM Caching
 		 */
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index dcbfdb99b6..4751886a45 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -295,7 +295,7 @@ chipsetinit (struct northbridge_amd_gx2_config *nb){
 	outb( P80_CHIPSET_INIT, 0x80);
 	ChipsetGeodeLinkInit();
 #if 0
-	/* we hope NEVER to be in linuxbios when S3 resumes 
+	/* we hope NEVER to be in coreboot when S3 resumes 
 	if (! IsS3Resume()) */
 	{
 		struct acpiinit *aci = acpi_init_table;
diff --git a/src/northbridge/intel/i855pm/raminit.c b/src/northbridge/intel/i855pm/raminit.c
index 07dac67a73..9a0f7c08d9 100644
--- a/src/northbridge/intel/i855pm/raminit.c
+++ b/src/northbridge/intel/i855pm/raminit.c
@@ -1358,7 +1358,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
 }
 
 
-	/* I have finally seen ram bad enough to cause LinuxBIOS
+	/* I have finally seen ram bad enough to cause coreboot
 	 * to die in mysterious ways, before booting up far
 	 * enough to run a memory tester.  This code attempts
 	 * to catch this blatantly bad ram, with a spot check.
diff --git a/src/northbridge/motorola/mpc107/Config.lb b/src/northbridge/motorola/mpc107/Config.lb
index 78fc99e85f..83e7b3d0b3 100644
--- a/src/northbridge/motorola/mpc107/Config.lb
+++ b/src/northbridge/motorola/mpc107/Config.lb
@@ -1,5 +1,5 @@
 #
-# Objects linked with linuxbios
+# Objects linked with coreboot
 #
 
 config chip.h
diff --git a/src/northbridge/motorola/mpc107/mpc107_northbridge.c b/src/northbridge/motorola/mpc107/mpc107_northbridge.c
index 7dcf7c89f8..7e692f039d 100644
--- a/src/northbridge/motorola/mpc107/mpc107_northbridge.c
+++ b/src/northbridge/motorola/mpc107/mpc107_northbridge.c
@@ -36,7 +36,7 @@ static void pci_domain_read_resources(device_t dev)
 /*
  * pci_domain_set_resources creates memory resources describing the
  * fixed memory on the system. This is not actually used anywhere
- * except when the linuxbios table is generated.
+ * except when the coreboot table is generated.
  */
 static void pci_domain_set_resources(device_t dev)
 {
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 89f0874b35..76d93f0ddb 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -121,7 +121,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* these are ENDING addresses, not sizes. 
 			 * if there is memory in this slot, then reg will be > rambits.
 			 * So we just take the max, that gives us total. 
-			 * We take the highest one to cover for once and future linuxbios
+			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index bd128b9cc9..e2bab04afe 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -158,7 +158,7 @@ static void vga_init(device_t dev)
 
 #else
 
-	/* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */
+	/* code to make vga init run in real mode - does work but against the current coreboot philosophy */
 	printk_debug("INSTALL REAL-MODE IDT\n");
         setup_realmode_idt();
         printk_debug("DO THE VGA BIOS\n");
@@ -293,7 +293,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* these are ENDING addresses, not sizes. 
 			 * if there is memory in this slot, then reg will be > rambits.
 			 * So we just take the max, that gives us total. 
-			 * We take the highest one to cover for once and future linuxbios
+			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index 5508e3e659..c543428216 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -28,7 +28,7 @@
 	256 Mb 266Mhz 2 Bank (i.e. double sided)
 	512 Mb 266Mhz 2 Bank (i.e. double sided)
 */
-/* ported and enhanced from assembler level code in Linuxbios v1 */
+/* ported and enhanced from assembler level code in coreboot v1 */
 
 #include <cpu/x86/mtrr.h>
 #include "raminit.h"
diff --git a/src/southbridge/amd/cs5530/cs5530_vga.c b/src/southbridge/amd/cs5530/cs5530_vga.c
index d60ce6ed6e..2dc8cf0b3b 100644
--- a/src/southbridge/amd/cs5530/cs5530_vga.c
+++ b/src/southbridge/amd/cs5530/cs5530_vga.c
@@ -448,7 +448,7 @@ static void show_boot_splash_16(u32 swidth, u32 sheight, u32 pitch,void *base)
 #endif
 
 /**
- * LinuxBIOS management part
+ * coreboot management part
  * @param[in] dev Info about the PCI device to initialise
  */
 static void cs5530_vga_init(device_t dev)
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 85d086a656..5c827f275f 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -511,7 +511,7 @@ void chipsetinit(void)
 
 	post_code(P80_CHIPSET_INIT);
 
-	/* we hope NEVER to be in linuxbios when S3 resumes
+	/* we hope NEVER to be in coreboot when S3 resumes
 	   if (! IsS3Resume()) */
 	{
 		struct acpiinit *aci = acpi_init_table;
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index 8167691dea..dd11810483 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -185,7 +185,7 @@ static void bcm5785_early_setup(void)
         byte |= (1<<0); // SATA enable
         pci_write_config8(dev, 0x84, byte);
 
-// wdt and cf9 for later in linuxbios_ram to call hard_reset
+// wdt and cf9 for later in coreboot_ram to call hard_reset
         bcm5785_enable_wdt_port_cf9();
 
         bcm5785_enable_msg();
diff --git a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
index c97dd63e2c..8d80135d5d 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
@@ -28,7 +28,7 @@ static inline void smbus_delay(void)
 	outb(0x80, 0x80);
 }
 
-// See http://openbios.org/pipermail/linuxbios/2004-September/009077.html
+// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
 // for a description of this function.
 static int smbus_wait_until_active(void)
 {
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index f3f4f1c947..b0f4de7e34 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -18,7 +18,7 @@
  * MA 02110-1301 USA
  */
 /* (C) Copyright 2005 Nick Barker <nick.barker@btinternet.com
-   brought into line with the current architecture of LinuxBios */ 
+   brought into line with the current architecture of coreboot */ 
 
 
 #include <arch/io.h>
diff --git a/src/stream/rom_stream.c b/src/stream/rom_stream.c
index 1b4d0e047a..39bae75b5b 100644
--- a/src/stream/rom_stream.c
+++ b/src/stream/rom_stream.c
@@ -84,7 +84,7 @@ int stream_init(void)
 		dest = (CONFIG_LB_MEM_TOPK<<10);
 	}
 #endif
-        if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { //linuxbios tables etc
+        if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { // coreboot tables etc
 	  dest = (unsigned char *) (CONFIG_LB_MEM_TOPK<<10);
         }
 #endif
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c
index ae00361ba3..06c026509f 100644
--- a/src/superio/smsc/lpc47n217/superio.c
+++ b/src/superio/smsc/lpc47n217/superio.c
@@ -22,7 +22,7 @@
  */
 
 /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
-/* Based on LinuxBIOS code for SMSC 47B397. */
+/* Based on coreboot code for SMSC 47B397. */
 
 #include <arch/io.h>
 #include <device/device.h>