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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-14 13:56:28 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-14 13:56:28 +0000 |
| commit | fd14d4414aab2b196bdf4499a3590187bf9c782d (patch) | |
| tree | 085d3c79e533b84464ab97ba8c409b2c83c990b8 /src | |
| parent | 73c92a4a7c1f9f0ff4451a5b34da9d18978e90e2 (diff) | |
| download | coreboot-fd14d4414aab2b196bdf4499a3590187bf9c782d.tar.xz | |
remove erroneous cache disable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/model_gx2/cpureginit.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c index 779669c34a..5e786910c5 100644 --- a/src/cpu/amd/model_gx2/cpureginit.c +++ b/src/cpu/amd/model_gx2/cpureginit.c @@ -231,9 +231,13 @@ cpuRegInit (void){ wrmsr(msrnum, msr); } -/* */ -/* Cache Overides*/ -/* */ +#if 0 + /* */ + /* Cache Overides*/ + /* */ + /* This code disables the data cache. Don't execute this + * unless you're testing something. + */ /* Allow NVRam to override DM Setup*/ /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/ { @@ -243,6 +247,9 @@ cpuRegInit (void){ msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; wrmsr(msrnum, msr); } + /* This code disables the instruction cache. Don't execute + * this unless you're testing something. + */ /* Allow NVRam to override IM Setup*/ /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/ { @@ -251,6 +258,7 @@ cpuRegInit (void){ msr.lo |= IM_CONFIG_LOWER_ICD_SET; wrmsr(msrnum, msr); } +#endif } |