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authorRonald G. Minnich <rminnich@gmail.com>2006-10-18 16:00:10 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-10-18 16:00:10 +0000
commitfd845a04a901475ad85472a94789c34f151cf541 (patch)
tree605c6a4ad48f085241231359ac32f65930188a3c /src
parent69fd463a1b2f774ab0628737242d4b414635d327 (diff)
downloadcoreboot-fd845a04a901475ad85472a94789c34f151cf541.tar.xz
add the CAFE IRQ support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/olpc/btest/mainboard.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/olpc/btest/mainboard.c b/src/mainboard/olpc/btest/mainboard.c
index 35826cb24d..922073c81d 100644
--- a/src/mainboard/olpc/btest/mainboard.c
+++ b/src/mainboard/olpc/btest/mainboard.c
@@ -68,6 +68,33 @@ static void init_dcon(void) {
write_bit(rev > 0 ? 1 : 0);
}
+void
+init_cafe_irq(void){
+ const unsigned char slots_cafe[4] = {11, 0, 0, 0};
+
+
+ /* CAFE PCI slots */
+ pci_assign_irqs(0, 0x0C, slots_cafe);
+
+ /* Make the pin assignments - NOTENOTENOTE: This should be
+ * configurable!
+ */
+
+ /* Configure the GPIO pins to use - class 0, index 9 to configure
+ * AB. Write 0xFF to disable
+ */
+
+ vrWrite(0x9, 0XFF00);
+
+ /* Configure the GPIO pins to use - class 0, index A to configure
+ * CD. Write 0xFF to disable
+ */
+
+ vrWrite(0xA, 0xFFFF);
+
+}
+
+
static void init(struct device *dev) {
/*
unsigned bus = 0;
@@ -94,6 +121,7 @@ static void init(struct device *dev) {
#endif
init_dcon();
+ init_cafe_irq();
printk_debug("OLPC BTEST EXIT %s\n", __FUNCTION__);
}