hdama mainboard and target.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 173 insertions, 0 deletions

diff --git a/targets/arima/hdama/Config.lb b/targets/arima/hdama/Config.lb
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+# Sample config file for Motorola Sandpoint X3 Demo Board with
+# the Arima HDAMA
+# This will make a target directory of ./hdama
+
+loadoptions
+
+target ./hdama
+
+uses CONFIG_COMPRESS
+uses CONFIG_IOAPIC
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses ENABLE_FIXED_AND_VARIABLE_MTRRS
+uses FINAL_MAINBOARD_FIXUP
+uses HAVE_FALLBACK_BOOT
+uses HAVE_PIRQ_TABLE
+uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAX_CPUS
+uses MEMORY_HOLE
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SECTION_SIZE
+uses ROM_SIZE
+uses SIO_BASE
+uses SIO_SYSTEM_CLK_INPUT
+uses STACK_SIZE
+uses USE_ELF_BOOT
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+
+### Customize our winbond superio chip for this motherboard
+###
+option SIO_BASE=0x2e
+option SIO_SYSTEM_CLK_INPUT=0
+#
+###
+### Build code for the fallback boot
+###
+option HAVE_FALLBACK_BOOT=1
+#
+###
+### Build code to export a programmable irq routing table
+###
+option HAVE_PIRQ_TABLE=1
+option IRQ_SLOT_COUNT=7
+#
+###
+### Build code for SMP support
+### Only worry about 2 micro processors
+###
+##option CONFIG_SMP=1
+option MAX_CPUS=1
+#
+###
+### Build code to setup a generic IOAPIC
+###
+option CONFIG_IOAPIC=1
+#
+###
+### MEMORY_HOLE instructs earlymtrr.inc to
+### enable caching from 0-640KB and to disable 
+### caching from 640KB-1MB using fixed MTRRs 
+###
+### Enabling this option breaks SMP because secondary
+### CPU identification depends on only variable MTRRs
+### being enabled.
+###
+option MEMORY_HOLE=0
+#
+###
+### Enable both fixed and variable MTRRS
+### When we setup MTRRs in mtrr.c  
+###
+### We must setup the fixed mtrrs or we confuse SMP secondary
+### processor identification
+###
+option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
+#
+###
+### Clean up the motherboard id strings
+###
+option MAINBOARD_PART_NUMBER="Solo7"
+option MAINBOARD_VENDOR="AMD"
+#
+###
+### Call the final_mainboard_fixup function
+###
+option FINAL_MAINBOARD_FIXUP=1
+option USE_FALLBACK_IMAGE=0
+
+###
+### Only use the option table in a normal image
+###
+option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
+#
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+if USE_FALLBACK_IMAGE 
+  option ROM_SECTION_SIZE  = FALLBACK_SIZE
+  option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
+end
+if USE_NORMAL_IMAGE
+  option ROM_SECTION_SIZE  = (ROM_SIZE - FALLBACK_SIZE)
+  option ROM_SECTION_OFFSET= 0
+end
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+option PAYLOAD_SIZE            = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+option CONFIG_ROM_STREAM     = 1
+#
+###
+### Compute where this copy of linuxBIOS will start in the boot rom
+###
+option _ROMBASE      = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
+#
+###
+### Compute a range of ROM that can cached to speed up linuxBIOS,
+### execution speed.
+###
+##expr XIP_ROM_SIZE = 65536
+##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
+##option XIP_ROM_SIZE=65536
+##option XIP_ROM_BASE=0xffff0000
+#
+## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
+##option XIP_ROM_SIZE=0x8000
+##option XIP_ROM_BASE=0xffff8000
+
+## We don't use compressed image
+option CONFIG_COMPRESS=0
+
+option USE_ELF_BOOT=1
+
+option ROM_SIZE=524288
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+option ROM_IMAGE_SIZE=49152
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x00100000
+
+##
+## Use a 64K stack
+##
+option STACK_SIZE=0x10000
+
+##
+## Use a 64K heap
+##
+option HEAP_SIZE=0x10000
+
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##       
+option ROM_SECTION_SIZE=ROM_SIZE
+option ROM_SECTION_OFFSET=0
+
+# Arima hdama
+mainboard arima/hdama
+	makedefine CFLAGS += -g
+end