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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-11-09 23:35:11 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-11-09 23:35:11 +0000 |
| commit | da754e0586297faf0d3b5c378dce4226913833bc (patch) | |
| tree | 7fd094bce40cf61ca414e088b045fc752118f3fe /targets/motorola | |
| parent | 2e52d92c20f83479ccb6d644ecf362bdbc2316ff (diff) | |
| download | coreboot-da754e0586297faf0d3b5c378dce4226913833bc.tar.xz | |
updated for v2
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets/motorola')
| -rw-r--r-- | targets/motorola/sandpoint/Config.lb | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/targets/motorola/sandpoint/Config.lb b/targets/motorola/sandpoint/Config.lb index 433d6518de..b725ab40de 100644 --- a/targets/motorola/sandpoint/Config.lb +++ b/targets/motorola/sandpoint/Config.lb @@ -6,15 +6,16 @@ loadoptions target sandpoint -uses ARCH CROSS_COMPILE +uses CROSS_COMPILE uses HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS uses DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_CHIP_CONFIGURE +uses CONFIG_USE_INIT uses NO_POST uses CONFIG_CONSOLE_SERIAL8250 uses TTYS0_BASE +uses UART0_IO_BASE uses CONFIG_IDE_STREAM uses IDE_BOOT_DRIVE uses IDE_SWAB IDE_OFFSET @@ -22,21 +23,17 @@ uses ROM_SIZE ROM_IMAGE_SIZE uses ROM_SECTION_SIZE uses ROM_SECTION_OFFSET uses _RESET +uses _EXCEPTION_VECTORS uses _ROMBASE uses _RAMBASE -uses CACHE_RAM_BASE -uses CACHE_RAM_SIZE uses STACK_SIZE HEAP_SIZE -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR ## use a cross compiler option CROSS_COMPILE="powerpc-eabi-" #option CROSS_COMPILE="ppc_74xx-" -## Use chip configuration -option CONFIG_CHIP_CONFIGURE=1 +## Use stage 1 initialization code +option CONFIG_USE_INIT=1 ## We don't use compressed image option CONFIG_COMPRESS=0 @@ -47,7 +44,8 @@ option NO_POST=1 ## Enable serial console option DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option TTYS0_BASE=0xfe000000 +option TTYS0_BASE=0x3f0 +option UART0_IO_BASE=0xfe000000+TTYS0_BASE ## Boot linux from IDE option CONFIG_IDE_STREAM=1 @@ -59,8 +57,8 @@ option ROM_SIZE=1048576 ## For the trick of using cache as ram ## put the fake ram location at this address -option CACHE_RAM_BASE=0x00200000 -option CACHE_RAM_SIZE=0x00004000 +#option CACHE_RAM_BASE=0x00200000 +#option CACHE_RAM_SIZE=0x00004000 ## ## Use a 64K stack @@ -83,6 +81,9 @@ romimage "normal" ## Sandpoint reset vector option _RESET=0xfff00100 + ## Excpetoion vectors + option _EXCEPTION_VECTORS=_RESET+0x100 + ## Start of linuxBIOS in the boot rom ## = _RESET + exeception vector table size option _ROMBASE=0xfff03100 |