diff options
| author | Marc Jones <marcj303@gmail.com> | 2009-03-20 16:36:05 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2009-03-20 16:36:05 +0000 |
| commit | 5dd4a20b96f2bb563ae724c4eaf2524529bc46d0 (patch) | |
| tree | bf2408d2ba042c23fee2d160fd6ce954f92a10c4 /targets/supermicro/h8dme/Config.lb | |
| parent | 2f4979f347ea7014786934cccab10772f6a6402a (diff) | |
| download | coreboot-5dd4a20b96f2bb563ae724c4eaf2524529bc46d0.tar.xz | |
Add Supermicro h8dm3 mainboard. This is mostly a copy from the h8dmr.
The one issues is the SPD address switch for the second CPU. That means that
the memory must be an exact match on each CPU.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets/supermicro/h8dme/Config.lb')
| -rw-r--r-- | targets/supermicro/h8dme/Config.lb | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/targets/supermicro/h8dme/Config.lb b/targets/supermicro/h8dme/Config.lb new file mode 100644 index 0000000000..de68f38fb7 --- /dev/null +++ b/targets/supermicro/h8dme/Config.lb @@ -0,0 +1,48 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target h8dme +mainboard supermicro/h8dme + +romimage "normal" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x40000 + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + payload ../payload.elf +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x40000 + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + payload ../payload.elf +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" |