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authorPeter Stuge <peter@stuge.se>2007-05-10 23:50:27 +0000
committerStefan Reinauer <stepan@openbios.org>2007-05-10 23:50:27 +0000
commitdeabf510bff37c1f3a1fd3ec50b88db17d38b802 (patch)
tree3dce82f996b72212c3143dd6f68f4d9ff93081de /targets
parentddf845f620eb43d9ea2e8b0b265c321c6e797e6f (diff)
downloadcoreboot-deabf510bff37c1f3a1fd3ec50b88db17d38b802.tar.xz
Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used for timer calibration, which takes about one second. All EPIA-M boards have timer2 so we use it to boot faster. Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO calibration but add the TSC options so that they can be set in Config.lb. src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we set HAVE_HARD_RESET=0 for both boards. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets')
-rw-r--r--targets/via/epia/Config.lb5
1 files changed, 5 insertions, 0 deletions
diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb
index e45fcf33d0..39f1a6b377 100644
--- a/targets/via/epia/Config.lb
+++ b/targets/via/epia/Config.lb
@@ -1,6 +1,11 @@
# Sample config file for EPIA
# This will make a target directory of ./epia
+## uncomment these three lines if you have a Nehemiah CPU to boot 1s faster
+#option CONFIG_UDELAY_IO=0
+#option CONFIG_UDELAY_TSC=1
+#option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
target epia
mainboard via/epia
option MAXIMUM_CONSOLE_LOGLEVEL=9