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authorStefan Reinauer <stepan@coresystems.de>2007-11-02 12:54:49 +0000
committerStefan Reinauer <stepan@openbios.org>2007-11-02 12:54:49 +0000
commit7162cf7278f1489cbe4b56a7fb95b713735387d9 (patch)
tree7ca1b3b27a16e3b7aa00584aaf93aa9a239ad97d /targets
parent894562f4eb81a83b360e3bd928a0517ae0122b4d (diff)
downloadcoreboot-7162cf7278f1489cbe4b56a7fb95b713735387d9.tar.xz
fix up iwill board compilation. Untested, trivial
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets')
-rw-r--r--targets/iwill/dk8x/Config.lb167
1 files changed, 167 insertions, 0 deletions
diff --git a/targets/iwill/dk8x/Config.lb b/targets/iwill/dk8x/Config.lb
new file mode 100644
index 0000000000..9ae39be8e8
--- /dev/null
+++ b/targets/iwill/dk8x/Config.lb
@@ -0,0 +1,167 @@
+# Sample config file for
+# the Iwill DK8X
+# This will make a target directory of ./dk8x
+
+target dk8x
+
+mainboard iwill/dk8x
+
+option HAVE_HARD_RESET=1
+
+option HAVE_OPTION_TABLE=1
+option HAVE_MP_TABLE=1
+option ROM_SIZE=1024*1024
+
+option HAVE_FALLBACK_BOOT=1
+
+#option CONFIG_LSI_SCSI_FW_FIXUP=1
+
+
+#
+###
+### Build code to export a programmable irq routing table
+###
+option HAVE_PIRQ_TABLE=1
+option IRQ_SLOT_COUNT=12
+#
+###
+### Build code for SMP support
+### Only worry about 2 micro processors
+###
+option CONFIG_SMP=1
+option CONFIG_MAX_CPUS=2
+#option CONFIG_LOGICAL_CPUS=2
+option CONFIG_MAX_PHYSICAL_CPUS=2
+#
+###
+### Build code to setup a generic IOAPIC
+###
+option CONFIG_IOAPIC=1
+#
+###
+### MEMORY_HOLE instructs earlymtrr.inc to
+### enable caching from 0-640KB and to disable
+### caching from 640KB-1MB using fixed MTRRs
+###
+### Enabling this option breaks SMP because secondary
+### CPU identification depends on only variable MTRRs
+### being enabled.
+###
+#option MEMORY_HOLE=0
+#
+###
+### Clean up the motherboard id strings
+###
+option MAINBOARD_PART_NUMBER="DK8X"
+option MAINBOARD_VENDOR="IWILL"
+#
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+#option FALLBACK_SIZE=524288
+#option FALLBACK_SIZE=98304
+option FALLBACK_SIZE=131072
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+option ROM_IMAGE_SIZE=65536
+
+
+###
+### Compute where this copy of linuxBIOS will start in the boot rom
+###
+#
+###
+
+## We do use compressed image
+#option CONFIG_COMPRESS=1
+
+option CONFIG_CONSOLE_SERIAL8250=1
+option TTYS0_BAUD=115200
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+option DEFAULT_CONSOLE_LOGLEVEL=7
+## At a maximum only compile in this level of debugging
+option MAXIMUM_CONSOLE_LOGLEVEL=7
+
+#option DEBUG=1
+
+#
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x004000
+
+##
+## Use a 32K stack
+##
+option STACK_SIZE=0x8000
+
+##
+## Use a 56K heap
+##
+option HEAP_SIZE=0xe000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+option CONFIG_ROM_PAYLOAD = 1
+
+#
+#
+romimage "normal"
+# 48K for SCSI FW
+# option ROM_SIZE = 512*1024-48*1024
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 512*1024-48*1024-48*1024
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option USE_FALLBACK_IMAGE=0
+ option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+ option ROM_SECTION_OFFSET= 0
+
+ option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+ option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+ option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+
+# option XIP_ROM_SIZE = FALLBACK_SIZE
+ option XIP_ROM_SIZE = 65536
+
+ option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+
+ payload /usr/src/filo-0.4.1_btext/filo.elf
+# payload /usr/src/filo-0.4.2/filo.elf
+end
+
+romimage "fallback"
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option USE_FALLBACK_IMAGE=1
+ option ROM_SECTION_SIZE = FALLBACK_SIZE
+ option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
+
+ option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+ option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+ option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+
+# option XIP_ROM_SIZE = FALLBACK_SIZE
+ option XIP_ROM_SIZE = 65536
+ option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+
+ payload ../../../payloads/filo.elf
+# payload /usr/src/filo-0.4.2/filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"