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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-17 16:34:02 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-18 01:45:56 +0100 |
| commit | eb960f1af93b55cbfb0d5f86343970ded151d3c7 (patch) | |
| tree | 9b179c29e4985a406662cbbabf80569b5e98e360 /util/autoport/bd82x6x.go | |
| parent | e4f9d5c70ae3396a0005de7ea10709e74f003980 (diff) | |
| download | coreboot-eb960f1af93b55cbfb0d5f86343970ded151d3c7.tar.xz | |
util/autoport: Use common gpio.c for bd82x6x
In accordance to change I8bd981c4696c174152cf41caefa6c083650d283a
change autoport as well, as suggested by Vladimir.
Change-Id: I7cdaa779c11fd3f791a3ad213c24d927b5da76b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13731
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'util/autoport/bd82x6x.go')
| -rw-r--r-- | util/autoport/bd82x6x.go | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 3db77a59dc..1252292930 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -40,7 +40,7 @@ func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { AddROMStageFile("gpio.c", "") - gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" + gpio.WriteString(`#include <southbridge/intel/common/gpio.h> `) adresses := [3][6]int{ @@ -294,7 +294,7 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> |