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| author | Iru Cai <mytbk920423@gmail.com> | 2019-01-12 17:43:14 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2020-05-13 21:18:24 +0800 |
| commit | b7e37fd69e0adfec24d90b97d17dc1f42ab9aae8 (patch) | |
| tree | 11ffc6a06a23d8f6e7a2c9876ac55cdbada547c7 /util/autoport/main.go | |
| parent | f0045eb373c5376510d111c5e1091134c186884e (diff) | |
| download | coreboot-b7e37fd69e0adfec24d90b97d17dc1f42ab9aae8.tar.xz | |
autoport: Add support for Haswell-LynxPoint platform
It can generate a working source code for Clevo W650SZ and Lenovo
ThinkPad T440p.
Patchset 11: some fix up for the current coreboot code and LP PCH
- calculate backlight frequency according in the latest Haswell
devicetree
- there's some small difference in reading flash chip size for LP PCH
- only output 8 USB ports for LP PCH
Unresolved issues:
- Should we use DxxIR registers from the machine running factory
firmware?
TODO:
- Support Lynx Point LP
- GPIO
- GPE support
- Detect and generate the lengths and locations of the USB2 ports
(need to read IOBP registers)
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Diffstat (limited to 'util/autoport/main.go')
| -rw-r--r-- | util/autoport/main.go | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/util/autoport/main.go b/util/autoport/main.go index b2334e2b62..2de5349a0c 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -224,6 +224,12 @@ func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { pcidev.ConfigDump[addr]) } +func RestoreDIRRoute(f *os.File, regname string, val uint16) { + fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n", + regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7), + 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7)) +} + func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", pcidev.Bus, pcidev.Dev, pcidev.Func, addr, |