diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-21 17:55:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:39:19 +0000 |
| commit | 7e6946a74c714ff109c35d97001b22c9e868aaea (patch) | |
| tree | 98899e89dc00f8e5504f06d84eb6dc44227b4c80 /util/autoport | |
| parent | d6c15d0c8c39015994a180da82c3e6f9538b42de (diff) | |
| download | coreboot-7e6946a74c714ff109c35d97001b22c9e868aaea.tar.xz | |
cpu/intel/model_206ax: Remove the notion of sockets
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/autoport')
| -rw-r--r-- | util/autoport/sandybridge.go | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 41ac96dc94..4c3bbe87b1 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -63,16 +63,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { Dev: 0, Children: []DevTreeNode{ { - Chip: "cpu/intel/socket_rPGA989", - Children: []DevTreeNode{ - { - Chip: "lapic", - Dev: 0, - }, - }, - }, - - { Chip: "cpu/intel/model_206ax", Comment: "FIXME: check all registers", Registers: map[string]string{ @@ -86,6 +76,10 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { }, Children: []DevTreeNode{ { + Chip: "lapic", + Dev: 0, + }, + { Chip: "lapic", Dev: 0xacac, Disabled: true, @@ -114,7 +108,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { /* FIXME:XX some configs are unsupported. */ KconfigBool["SANDYBRIDGE_IVYBRIDGE_LVDS"] = true - KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true KconfigBool["USE_NATIVE_RAMINIT"] = true KconfigBool["INTEL_INT15"] = true |