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authorNico Huber <nico.h@gmx.de>2020-03-22 20:12:13 +0100
committerNico Huber <nico.h@gmx.de>2020-03-24 20:36:36 +0000
commitd07ac8ee13ce7f1af5a9d9a5d2e194ab27b8fb9a (patch)
tree018e611167eebe530fe3e56656d8e9adea25c911 /util/autoport
parente47132be6601bfd485076d6520e56a8b8ecb0737 (diff)
downloadcoreboot-d07ac8ee13ce7f1af5a9d9a5d2e194ab27b8fb9a.tar.xz
drivers/intel/gma: Ditch `link_frequency_270_mhz` setting
The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/autoport')
-rw-r--r--util/autoport/sandybridge.go21
1 files changed, 0 insertions, 21 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index acfda6b8dd..a64ef7a4c2 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -14,26 +14,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
`)
- pchLVDS := inteltool.IGD[0xe1180]
- dualChannel := pchLVDS&(3<<2) == (3 << 2)
- pipe := (pchLVDS >> 30) & 1
- link_m1 := inteltool.IGD[0x60040+0x1000*pipe]
- link_n1 := inteltool.IGD[0x60044+0x1000*pipe]
- link_factor := float32(link_m1) / float32(link_n1)
- fp0 := inteltool.IGD[0xc6040+8*pipe]
- dpll := inteltool.IGD[0xc6014+4*pipe]
- pixel_m2 := fp0 & 0xff
- pixel_m1 := (fp0>>8)&0xff + 2
- pixel_p1 := uint32(1)
- for i := dpll & 0x1ffff; i != 0 && i&1 == 0; i >>= 1 {
- pixel_p1++
- }
- pixel_n := ((fp0 >> 16) & 0xff) + 2
- pixel_frequency := float32(120000*(5*pixel_m1+pixel_m2)) / float32(pixel_n*pixel_p1*7.0)
- if !dualChannel {
- pixel_frequency /= 2
- }
- link_frequency := pixel_frequency / link_factor
DevTree = DevTreeNode{
Chip: "northbridge/intel/sandybridge",
MissingParent: "northbridge",
@@ -51,7 +31,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
- "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
},
Children: []DevTreeNode{
{