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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-08-07 15:27:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-09-01 12:32:36 +0000 |
| commit | f3e23a313558b1e9e913878d7a638ff32321a4b3 (patch) | |
| tree | 12064c039d78bcb9e7f4bab4c986d533a7659b81 /util/crossgcc/patches/gcc-6.3.0_riscv.patch | |
| parent | d37ebddfd84699464d076642f35fce0ef21cd1d5 (diff) | |
| download | coreboot-f3e23a313558b1e9e913878d7a638ff32321a4b3.tar.xz | |
buildgcc: Integrate nds32 update from Andes Technology
This patch has been provided by Mentor Chih-Chyang Chang
on behalf of Andes Technology. It fixes using the coreboot
toolchain to compile the Chrome EC code base on the ITE8320
embedded controller.
The new patch incorporates a fix for the issue previously
fixed by patches/gcc-6.3.0_nds32.patch, so that patch can
be removed.
patches/gcc-6.3.0_riscv.patch needs to be slightly adjusted
to still apply cleanly (configure scripts only).
Change-Id: I0033888360f13ba951b692b3242aab6697ca61b3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'util/crossgcc/patches/gcc-6.3.0_riscv.patch')
| -rw-r--r-- | util/crossgcc/patches/gcc-6.3.0_riscv.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/util/crossgcc/patches/gcc-6.3.0_riscv.patch b/util/crossgcc/patches/gcc-6.3.0_riscv.patch index ca9555de0b..a60511362a 100644 --- a/util/crossgcc/patches/gcc-6.3.0_riscv.patch +++ b/util/crossgcc/patches/gcc-6.3.0_riscv.patch @@ -9030,9 +9030,9 @@ index c9e43fb80e3..5359a4e6ee5 100755 # version to the per-target configury. case "$cpu_type" in aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ -- | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \ +- | mips | nds32 | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \ - | visium | xstormy16 | xtensa) -+ | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \ ++ | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \ + | tilepro | visium | xstormy16 | xtensa) insn="nop" ;; @@ -9063,9 +9063,9 @@ index 33f9a0ecdc6..673fb1bb891 100644 # version to the per-target configury. case "$cpu_type" in aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ -- | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \ +- | mips | nds32 | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \ - | visium | xstormy16 | xtensa) -+ | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \ ++ | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \ + | tilepro | visium | xstormy16 | xtensa) insn="nop" ;; |