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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-02-23 14:43:39 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-03-04 17:35:13 +0100 |
| commit | 0da186c3ffb1d9aa7433a5d0d5263aba7a25ad60 (patch) | |
| tree | bc766e52206f4cf2f3feeda7f06b45a8a45b7dc4 /util/crossgcc/sum | |
| parent | d55ea7b69e2aaa77ff15da0e26a4dbdcce8ac81d (diff) | |
| download | coreboot-0da186c3ffb1d9aa7433a5d0d5263aba7a25ad60.tar.xz | |
soc/intel/skylake: indicate voltage margining enabled/disabled
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/crossgcc/sum')
0 files changed, 0 insertions, 0 deletions