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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-01-13 14:01:42 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-17 17:59:45 +0100 |
| commit | 8b89252f8ad2a79e8bdffc2abf250fc7110f3884 (patch) | |
| tree | 88c75f5a9496f8af06c7d7f5868370bd3db51358 /util/crossgcc | |
| parent | 01ba8cf7a78419eb1ac3c98ad33656b8925ef565 (diff) | |
| download | coreboot-8b89252f8ad2a79e8bdffc2abf250fc7110f3884.tar.xz | |
mainboard/google/reef: Ignore SPI IOSTANDBY
SPI controller need to access flash descriptors/SFDP during s0ix exit,
so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
GPIO_106.
BUG=chrome-os-partner:61370
BRANCH=reef
TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
content.
Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/18137
Tested-by: build bot (Jenkins)
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/crossgcc')
0 files changed, 0 insertions, 0 deletions