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| author | Jason Wang <Qingpei.Wang@amd.com> | 2008-11-28 21:36:51 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-11-28 21:36:51 +0000 |
| commit | f22ce41840ae966a6f465e90c8f05aed9ae5ef6b (patch) | |
| tree | 8cdef566a6d0c3449ab8f12adad0f05e5c6bd4ab /util/flashrom/flash.h | |
| parent | 4ed326be5d7dec9ee16190847ea0b9f42117fe1a (diff) | |
| download | coreboot-f22ce41840ae966a6f465e90c8f05aed9ae5ef6b.tar.xz | |
Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/flash.h')
| -rw-r--r-- | util/flashrom/flash.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/util/flashrom/flash.h b/util/flashrom/flash.h index d1e417fb39..cbc2e48a87 100644 --- a/util/flashrom/flash.h +++ b/util/flashrom/flash.h @@ -414,6 +414,7 @@ typedef enum { BUS_TYPE_ICH7_SPI, BUS_TYPE_ICH9_SPI, BUS_TYPE_IT87XX_SPI, + BUS_TYPE_SB600_SPI, BUS_TYPE_VIA_SPI } flashbus_t; @@ -497,6 +498,14 @@ int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf); +/* sb600spi.c */ +int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int sb600_spi_read(struct flashchip *flash, uint8_t *buf); +int sb600_spi_write(struct flashchip *flash, uint8_t *buf); +uint8_t sb600_read_status_register(void); +extern uint8_t volatile *sb600_spibar; + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(volatile uint8_t *dst); |