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authorPeter Stuge <peter@stuge.se>2008-01-25 01:52:45 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-01-25 01:52:45 +0000
commitf2a2a5ee2e498d648e00ac6af1ed859be6c194ea (patch)
tree7714eb19cc54a4278df72bb384edfcf2c9cde0a5 /util/flashrom/flash.h
parent14a3af111d5fa6bd72dc1cb4e457f70f23ce507b (diff)
downloadcoreboot-f2a2a5ee2e498d648e00ac6af1ed859be6c194ea.tar.xz
Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
working. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/flash.h')
-rw-r--r--util/flashrom/flash.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/util/flashrom/flash.h b/util/flashrom/flash.h
index 048f7440f0..dc30f717cf 100644
--- a/util/flashrom/flash.h
+++ b/util/flashrom/flash.h
@@ -166,6 +166,14 @@ extern struct flashchip flashchips[];
#define SHARP_LHF00L04 0xCF
/*
+ * Spansion was previously a joint venture of AMD and Fujitsu.
+ * S25 chips are SPI. The first device ID byte is memory type and
+ * the second device ID byte is memory capacity.
+ */
+#define SPANSION_ID 0x01 /* Spansion */
+#define SPANSION_S25FL016A 0x0214
+
+/*
* SST25 chips are SPI, first byte of device ID is memory type, second
* byte of device ID is related to log(bitsize) at least for some chips.
*/