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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-05-15 03:19:49 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-05-15 03:19:49 +0000 |
| commit | a4868c44b56424d3f0c28ad1a6aa95bdd7eae04b (patch) | |
| tree | 2c2ae700648ed4075c83e65f89fa6d62ee161f8b /util/flashrom/flash.h | |
| parent | c7d29013db37b25e842d5208d0c5664282715055 (diff) | |
| download | coreboot-a4868c44b56424d3f0c28ad1a6aa95bdd7eae04b.tar.xz | |
Add support for the JEDEC RES (Read Electronic Signature and Resume from
Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/flash.h')
| -rw-r--r-- | util/flashrom/flash.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/util/flashrom/flash.h b/util/flashrom/flash.h index 4f73e0d1da..5d7b64508c 100644 --- a/util/flashrom/flash.h +++ b/util/flashrom/flash.h @@ -177,6 +177,8 @@ extern struct flashchip flashchips[]; /* * MX25 chips are SPI, first byte of device ID is memory type, * second byte of device ID is log(bitsize)-9. + * Generalplus SPI chips seem to be compatible with Macronix + * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ #define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ @@ -266,6 +268,7 @@ extern struct flashchip flashchips[]; #define ST_M25P10A 0x2011 #define ST_M25P20 0x2012 #define ST_M25P40 0x2013 +#define ST_M25P40_RES 0x12 #define ST_M25P80 0x2014 #define ST_M25P16 0x2015 #define ST_M25P32 0x2016 @@ -366,7 +369,8 @@ int coreboot_init(void); extern char *lb_part, *lb_vendor; /* spi.c */ -int probe_spi(struct flashchip *flash); +int probe_spi_rdid(struct flashchip *flash); +int probe_spi_res(struct flashchip *flash); int it87xx_probe_spi_flash(const char *name); int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void spi_write_enable(); |