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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-03-14 17:20:59 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-03-14 17:20:59 +0000 |
| commit | ae8a08df3b477d950860915686650de5fff330d1 (patch) | |
| tree | 08f57943a4e6989de862173d2005bcd0e44d6b21 /util/flashrom/flashchips.c | |
| parent | 0b202d0a6ebfda908284edf109ad0baf3cb4cb95 (diff) | |
| download | coreboot-ae8a08df3b477d950860915686650de5fff330d1.tar.xz | |
Prepare for ICH7/ICH8 SPI support by adding some debugging for all
ICH* chipsets. Functionality (except printing) should be unchanged.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/flashchips.c')
0 files changed, 0 insertions, 0 deletions