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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-10-18 00:24:07 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-10-18 00:24:07 +0000 |
| commit | 79aa01a6c35bfa03ae8010b7044e878d38589e89 (patch) | |
| tree | f64c7d221629f3527e2c82897d27de3b39cd8fc8 /util/flashrom/flashchips.c | |
| parent | dcb9abdf4ce76910191c5b3abf56d03ad800e1f7 (diff) | |
| download | coreboot-79aa01a6c35bfa03ae8010b7044e878d38589e89.tar.xz | |
Add generic SPI flash erase and write support to flashrom. The first
chip the code was tested and verified with is the Macronix MX25L4005,
but other chips should work as well.
Timeouts are still hardcoded to data sheet maxima, but the status
register checking code is already there.
Thanks to Harald Gutmann for the initial code on which this is loosely
based.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/flashchips.c')
| -rw-r--r-- | util/flashrom/flashchips.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/flashrom/flashchips.c b/util/flashrom/flashchips.c index 0c393a9f4e..d1b471a240 100644 --- a/util/flashrom/flashchips.c +++ b/util/flashrom/flashchips.c @@ -39,7 +39,7 @@ struct flashchip flashchips[] = { {"Mx29f002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024, - probe_spi, NULL, NULL}, + probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, |