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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-11-15 13:55:43 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-11-15 13:55:43 +0000 |
| commit | ef3f7e38eae30f733039b06df7da090bc4a0ed67 (patch) | |
| tree | fdb600f8566d704f8dd8a4329ddbefef984002cc /util/flashrom/spi.h | |
| parent | 385e90ad1c305473ff34c22199f8cdf141669027 (diff) | |
| download | coreboot-ef3f7e38eae30f733039b06df7da090bc4a0ed67.tar.xz | |
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.
Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D
Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642
Add the ID, but no probing function for this chip:
AT25F512A
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/spi.h')
| -rw-r--r-- | util/flashrom/spi.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/flashrom/spi.h b/util/flashrom/spi.h index 429ca6f013..54c71fc668 100644 --- a/util/flashrom/spi.h +++ b/util/flashrom/spi.h @@ -54,7 +54,7 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 -/* Block Erase 0x52 is supported by SST chips. */ +/* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00 |