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authorUrja Rannikko <urjaman@gmail.com>2008-10-18 13:54:30 +0000
committerPeter Stuge <peter@stuge.se>2008-10-18 13:54:30 +0000
commit582364d8089cb630e673eaee3710733b11d5125b (patch)
tree2e89e5e3a45bcc976dc558f0f08ef16a59f9d253 /util/flashrom
parent71a2fbf9d531a3e97660e60d384c1ed15191f54f (diff)
downloadcoreboot-582364d8089cb630e673eaee3710733b11d5125b.tar.xz
flashrom: Allow the SiS 620 chipset to detect and read at least 256kb chips.
Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom')
-rw-r--r--util/flashrom/chipset_enable.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c
index 22c40dffb2..3ad99cc750 100644
--- a/util/flashrom/chipset_enable.c
+++ b/util/flashrom/chipset_enable.c
@@ -540,6 +540,17 @@ static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
return -1;
}
+ /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
+ new = pci_read_byte(dev,0x40);
+ new &= 0xFB;
+ new |= 0x3;
+ pci_write_byte(dev,0x40,new);
+ newer = pci_read_byte(dev,0x40);
+ if (newer != new) {
+ printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
+ printf("Stuck at 0x%x\n", newer);
+ return -1;
+ }
return 0;
}