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authorEd Swierk <eswierk@arastra.com>2008-08-20 20:31:41 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-08-20 20:31:41 +0000
commit4b461b6b78c47f6fc32a94f2141dd1847eeed8da (patch)
tree1c636fb93a59ddce0a598be934a0a8b8c3e6af70 /util/flashrom
parent2319027d7e3a9b44110794a553b10a554fed1102 (diff)
downloadcoreboot-4b461b6b78c47f6fc32a94f2141dd1847eeed8da.tar.xz
flashrom: Recognize the Intel EP80579 LPC flash interface.
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom')
-rw-r--r--util/flashrom/chipset_enable.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c
index 95565ce22a..241a69831b 100644
--- a/util/flashrom/chipset_enable.c
+++ b/util/flashrom/chipset_enable.c
@@ -707,6 +707,7 @@ static const FLASH_ENABLE enables[] = {
{0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
{0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
{0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
+ {0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc},
{0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
{0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
{0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},