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authorMats Erik Andersson <mats.andersson@gisladisker.se>2008-09-26 13:19:02 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-09-26 13:19:02 +0000
commitad9bdb4345d73c7e9ae53b4bef4796d4216c34a2 (patch)
tree5e4d755249316df47c2f40a882ccacf4ccf40699 /util/flashrom
parent6c55b05cb2f910d5bb2823f5457de8cae3b43271 (diff)
downloadcoreboot-ad9bdb4345d73c7e9ae53b4bef4796d4216c34a2.tar.xz
Activate proper support for EN29F002(A)(N)[BT].
Fully tested for Probe/Read/Erase/Write on EN29F002NT. Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()' are still in use, but a tailored 'write_en29f002a()' is needed due to a byte wise writing mechanism for this chip. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom')
-rw-r--r--util/flashrom/Makefile2
-rw-r--r--util/flashrom/en29f002a.c53
-rw-r--r--util/flashrom/flash.h5
-rw-r--r--util/flashrom/flashchips.c4
4 files changed, 54 insertions, 10 deletions
diff --git a/util/flashrom/Makefile b/util/flashrom/Makefile
index b3ed739f67..09c68dedf1 100644
--- a/util/flashrom/Makefile
+++ b/util/flashrom/Makefile
@@ -26,7 +26,7 @@ endif
OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \
sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \
- w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o \
+ w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \
sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \
flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \
ichspi.o w39v040c.o
diff --git a/util/flashrom/en29f002a.c b/util/flashrom/en29f002a.c
index e2b4f9b09b..904b58b819 100644
--- a/util/flashrom/en29f002a.c
+++ b/util/flashrom/en29f002a.c
@@ -19,12 +19,17 @@
*/
/*
- EN29F512 has 1C,21
- EN29F010 has 1C,20
- EN29F040A has 1C,04
- EN29LV010 has 1C,6E and uses short F0 reset sequence
- EN29LV040(A) has 1C,4F and uses short F0 reset sequence
+ * EN29F512 has 1C,21
+ * EN29F010 has 1C,20
+ * EN29F040A has 1C,04
+ * EN29LV010 has 1C,6E and uses short F0 reset sequence
+ * EN29LV040(A) has 1C,4F and uses short F0 reset sequence
*/
+
+#include <stdio.h>
+#include <stdint.h>
+#include "flash.h"
+
int probe_en29f512(struct flashchip *flash)
{
volatile uint8_t *bios = flash->virtual_memory;
@@ -53,9 +58,11 @@ int probe_en29f512(struct flashchip *flash)
}
/*
- EN29F002AT has 1C,92
- EN29F002AB has 1C,97
+ * EN29F002AT has 1C,92
+ * EN29F002AB has 1C,97
*/
+
+/* This does not seem to function properly for EN29F002NT. */
int probe_en29f002a(struct flashchip *flash)
{
volatile uint8_t *bios = flash->virtual_memory;
@@ -83,3 +90,35 @@ int probe_en29f002a(struct flashchip *flash)
return 0;
}
+/* The EN29F002 chip needs repeated single byte writing, no block writing. */
+int write_en29f002a(struct flashchip *flash, uint8_t *buf)
+{
+ int i;
+ int total_size = flash->total_size * 1024;
+ volatile uint8_t *bios = flash->virtual_memory;
+ volatile uint8_t *dst = bios;
+
+ // *bios = 0xF0;
+ myusec_delay(10);
+ erase_chip_jedec(flash);
+
+ printf("Programming page: ");
+ for (i = 0; i < total_size; i++) {
+ /* write to the sector */
+ if ((i & 0xfff) == 0)
+ printf("address: 0x%08lx", (unsigned long)i);
+ *(bios + 0x5555) = 0xAA;
+ *(bios + 0x2AAA) = 0x55;
+ *(bios + 0x5555) = 0xA0;
+ *dst++ = *buf++;
+
+ /* wait for Toggle bit ready */
+ toggle_ready_jedec(dst);
+
+ if ((i & 0xfff) == 0)
+ printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
+ }
+
+ printf("\n");
+ return 0;
+}
diff --git a/util/flashrom/flash.h b/util/flashrom/flash.h
index 7e1fab7eb3..1dcdbfbdb5 100644
--- a/util/flashrom/flash.h
+++ b/util/flashrom/flash.h
@@ -435,6 +435,11 @@ int probe_29f040b(struct flashchip *flash);
int erase_29f040b(struct flashchip *flash);
int write_29f040b(struct flashchip *flash, uint8_t *buf);
+/* en29f002a.c */
+int probe_en29f002a(struct flashchip *flash);
+int erase_en29f002a(struct flashchip *flash);
+int write_en29f002a(struct flashchip *flash, uint8_t *buf);
+
/* ichspi.c */
int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
int ich_spi_read(struct flashchip *flash, uint8_t * buf);
diff --git a/util/flashrom/flashchips.c b/util/flashrom/flashchips.c
index 07445bf4ea..afe0bfbc4e 100644
--- a/util/flashrom/flashchips.c
+++ b/util/flashrom/flashchips.c
@@ -47,8 +47,8 @@ struct flashchip flashchips[] = {
{"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b},
{"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, 512, 64 * 1024, TEST_OK_PREW, probe_49fl00x, erase_49fl00x, write_49fl00x},
{"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002},
- {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},
- {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},
+ {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_en29f002a},
+ {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_en29f002a},
{"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, TEST_UNTESTED, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt},
{"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab},
{"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab},