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authorStefan Reinauer <stepan@coresystems.de>2007-06-05 10:28:39 +0000
committerStefan Reinauer <stepan@openbios.org>2007-06-05 10:28:39 +0000
commit444e39ee6d0a0458d751e48db33380af2dcad7d1 (patch)
treeeb844d0c0262fc84a8b07d437434be24640d046e /util/flashrom
parent973b0680a1e9cb76d90a4c1499d6041f71440ad9 (diff)
downloadcoreboot-444e39ee6d0a0458d751e48db33380af2dcad7d1.tar.xz
Add support for BCM HT1000 chipset to flashrom. Tested on IBM x3455.
(trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom')
-rw-r--r--util/flashrom/chipset_enable.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c
index bef55b147e..b663295770 100644
--- a/util/flashrom/chipset_enable.c
+++ b/util/flashrom/chipset_enable.c
@@ -387,6 +387,28 @@ static int enable_flash_mcp55(struct pci_dev *dev, char *name)
}
+
+static int enable_flash_ht1000(struct pci_dev *dev, char *name)
+{
+ unsigned char byte;
+
+ /* Set the 4MB enable bit */
+ byte = pci_read_byte(dev, 0x41);
+ byte |= 0x0e;
+ pci_write_byte(dev, 0x41, byte);
+
+ byte = pci_read_byte(dev, 0x43);
+ byte |= (1<<4);
+ pci_write_byte(dev, 0x43, byte);
+
+ /* Some magic. Comment me if you can */
+ outb(0x45, 0xcd6);
+ byte = inb(0xcd7);
+ outb(reg8|0x20, 0xcd7);
+
+ return 0;
+}
+
typedef struct penable {
unsigned short vendor, device;
char *name;
@@ -444,6 +466,8 @@ static FLASH_ENABLE enables[] = {
{0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
+
+ {0x1166, 0x0205, "BCM HT1000", enable_flash_ht1000},
};
/*